Module: Mesa Branch: master Commit: ff3f775476a907cd9410572d11e38b6c29e5e062 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff3f775476a907cd9410572d11e38b6c29e5e062
Author: Samuel Pitoiset <[email protected]> Date: Thu Apr 23 12:36:21 2020 +0200 radv: simplify checking for Navi1x chips Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4702> --- src/amd/vulkan/radv_cmd_buffer.c | 4 +--- src/amd/vulkan/radv_nir_to_llvm.c | 6 ++---- src/amd/vulkan/radv_pipeline.c | 4 +--- src/amd/vulkan/si_cmd_buffer.c | 4 +--- 4 files changed, 5 insertions(+), 13 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 6e5809ac492..a2526186e76 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3870,9 +3870,7 @@ void radv_CmdBindPipeline( /* Prefetch all pipeline shaders at first draw time. */ cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS; - if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 || - cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 || - cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) && + if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 && cmd_buffer->state.emitted_pipeline && radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) && !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) { diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 29a891627f7..e707ba8c907 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -1892,12 +1892,10 @@ radv_llvm_export_vs(struct radv_shader_context *ctx, outinfo->pos_exports++; } - /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang. + /* GFX10 skip POS0 exports if EXEC=0 and DONE=0, causing a hang. * Setting valid_mask=1 prevents it and has no other effect. */ - if (ctx->ac.family == CHIP_NAVI10 || - ctx->ac.family == CHIP_NAVI12 || - ctx->ac.family == CHIP_NAVI14) + if (ctx->ac.chip_class == GFX10) pos_args[0].valid_mask = 1; pos_idx = 0; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 448cbebf2ad..984a095aad8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4082,9 +4082,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, * * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5 */ - if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 || - pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 || - pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) && + if (pipeline->device->physical_device->rad_info.chip_class == GFX10 && !radv_pipeline_has_tess(pipeline) && ngg_state->hw_max_esverts != 256) { ge_cntl &= C_03096C_VERT_GRP_SIZE; diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 43d288145d7..a9083f33f7b 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -416,9 +416,7 @@ si_emit_graphics(struct radv_physical_device *physical_device, S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1)); radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0); - if (physical_device->rad_info.family == CHIP_NAVI10 || - physical_device->rad_info.family == CHIP_NAVI12 || - physical_device->rad_info.family == CHIP_NAVI14) { + if (physical_device->rad_info.chip_class == GFX10) { /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
