Module: Mesa Branch: master Commit: d56b8c45547086ce23873a58de58484f59ad3a9a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d56b8c45547086ce23873a58de58484f59ad3a9a
Author: Rob Clark <[email protected]> Date: Thu Apr 30 10:12:28 2020 -0700 freedreno: sync registers with envytools Pull in the `SP_xS_BRANCH_COND` regs to keep the mesa and envytools copies from getting out of sync. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813> --- src/freedreno/registers/a6xx.xml | 28 +++++++++++++++++------- src/freedreno/vulkan/tu_pipeline.c | 4 ++-- src/gallium/drivers/freedreno/a6xx/fd6_program.c | 4 ++-- 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml index b8c7746f218..fdb091c5b56 100644 --- a/src/freedreno/registers/a6xx.xml +++ b/src/freedreno/registers/a6xx.xml @@ -2819,6 +2819,12 @@ to upconvert to 32b float internally? </bitset> <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"> + <!-- + bitmask of true/false conditions for VS brac.N instructions, + bit N corresponds to brac.N + --> + </reg32> <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL"> <!-- # of VS outputs including pos/psize --> <bitfield name="VSOUT" low="0" high="5" type="uint"/> @@ -2893,7 +2899,15 @@ to upconvert to 32b float internally? <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/> <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> - <reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/> + <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE"> + <!-- size of output of previous stage --> + </reg32> + <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex"> + <!-- + bitmask of true/false conditions for FS brac.N instructions, + bit N corresponds to brac.N + --> + </reg32> <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS"> <!-- # of VS outputs including pos/psize --> @@ -2943,13 +2957,11 @@ to upconvert to 32b float internally? <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/> <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> - <reg32 offset="0xa981" name="SP_UNKNOWN_A981"> - <bitfield name="FACE0" pos="0" type="boolean"/> - <bitfield name="FACE1" pos="1" type="boolean"/> - <bitfield name="FACE2" pos="2" type="boolean"/> - <bitfield name="FACE3" pos="3" type="boolean"/> - <bitfield name="FACE4" pos="4" type="boolean"/> - <bitfield name="FACE5" pos="5" type="boolean"/> + <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"> + <!-- + bitmask of true/false conditions for FS brac.N instructions, + bit N corresponds to brac.N + --> </reg32> <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/> <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/> diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index 965cb5af264..1e376a120b5 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -648,7 +648,7 @@ tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader, const struct ir3_shader_variant *gs) { bool has_gs = gs->type != MESA_SHADER_NONE; - tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1); tu_cs_emit(cs, 0); tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2); @@ -1080,7 +1080,7 @@ tu6_emit_vpc(struct tu_cs *cs, tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1); tu_cs_emit(cs, 0); - tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1); tu_cs_emit(cs, vs->shader->output_size); } diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index 80eb0c8b988..454b4c4f9c7 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -772,12 +772,12 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1); OUT_RING(ring, 0); - OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1); + OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1); OUT_RING(ring, prev->shader->output_size); } else { OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1); OUT_RING(ring, 0); - OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1); + OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1); OUT_RING(ring, 0); } _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
