Module: Mesa Branch: master Commit: 7ae2110e61fb0f8cf70dd9abf8c14df050381c05 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ae2110e61fb0f8cf70dd9abf8c14df050381c05
Author: Alyssa Rosenzweig <[email protected]> Date: Fri Jun 12 12:22:54 2020 -0400 pan/mdg: Prefer type over regmode for schedule constraints Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5443> --- src/panfrost/midgard/midgard_schedule.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index 114a8de3211..9dee152c5e4 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -198,12 +198,12 @@ mir_is_scalar(midgard_instruction *ains) /* Otherwise, check mode hazards */ bool could_scalar = true; + unsigned szd = nir_alu_type_get_type_size(ains->dest_type); unsigned sz0 = nir_alu_type_get_type_size(ains->src_types[0]); unsigned sz1 = nir_alu_type_get_type_size(ains->src_types[1]); /* Only 16/32-bit can run on a scalar unit */ - could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8; - could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64; + could_scalar &= (szd == 16) || (szd == 32); if (ains->src[0] != ~0) could_scalar &= (sz0 == 16) || (sz0 == 32); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
