Module: Mesa Branch: master Commit: 575ab303a80d02fb7eda451f636e013e2d95fa60 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=575ab303a80d02fb7eda451f636e013e2d95fa60
Author: Elie Tournier <[email protected]> Date: Thu Jul 16 13:41:15 2020 +0100 virgl: set PIPE_CAP_BLEND_EQUATION_ADVANCED Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5516> --- src/gallium/drivers/virgl/virgl_screen.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index 3591762c9e3..348575d7b9f 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -262,6 +262,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_FBFETCH: return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0; + case PIPE_CAP_BLEND_EQUATION_ADVANCED: + return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION; case PIPE_CAP_TGSI_CLOCK: return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK; case PIPE_CAP_TGSI_ARRAY_COMPONENTS: _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
