Module: Mesa Branch: master Commit: 1b3be07b5faf867f698668080b060a270c5f795e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b3be07b5faf867f698668080b060a270c5f795e
Author: Daniel Schürmann <[email protected]> Date: Thu Jul 23 09:58:11 2020 +0200 aco: ensure readfirstlane subdword operands are always dword aligned Cc: 20.1 <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6024> --- src/amd/compiler/aco_register_allocation.cpp | 3 +++ src/amd/compiler/aco_validate.cpp | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 2fd8d3d66d5..862b00d859b 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -318,6 +318,9 @@ void print_regs(ra_ctx& ctx, bool vgprs, RegisterFile& reg_file) unsigned get_subdword_operand_stride(chip_class chip, const aco_ptr<Instruction>& instr, unsigned idx, RegClass rc) { + /* v_readfirstlane_b32 cannot use SDWA */ + if (instr->opcode == aco_opcode::p_as_uniform) + return 4; if (instr->format == Format::PSEUDO && chip >= GFX8) return rc.bytes() % 2 == 0 ? 2 : 1; diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index e532cdf241f..97967aac9c1 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -483,6 +483,8 @@ bool validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& inst Operand op = instr->operands[index]; unsigned byte = op.physReg().byte(); + if (instr->opcode == aco_opcode::p_as_uniform) + return byte == 0; if (instr->format == Format::PSEUDO && chip >= GFX8) return true; if (instr->isSDWA() && (static_cast<SDWA_instruction *>(instr.get())->sel[index] & sdwa_asuint) == (sdwa_isra | op.bytes())) _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
