Module: Mesa Branch: master Commit: 3d5bed0e883217242a4357116399f60486580170 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d5bed0e883217242a4357116399f60486580170
Author: Qiang Yu <[email protected]> Date: Thu Sep 3 11:30:28 2020 +0800 radeonsi: fix user fence space when MCBP is enabled When MCBP is enabled, IB maybe preempted which will also update the preempted fence field of the user fence. So we need to reserve enough space for each user fence. Fixes: 89d2dac5548 "radeonsi: enable preemption if the kernel enabled it" Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6577> --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index f51c7782033..c531d72ca45 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -1683,8 +1683,14 @@ finalize: /* Success. */ uint64_t *user_fence = NULL; + /* Need to reserve 4 QWORD for user fence: + * QWORD[0]: completed fence + * QWORD[1]: preempted fence + * QWORD[2]: reset fence + * QWORD[3]: preempted then reset + **/ if (has_user_fence) - user_fence = acs->ctx->user_fence_cpu_address_base + acs->ring_type; + user_fence = acs->ctx->user_fence_cpu_address_base + acs->ring_type * 4; amdgpu_fence_submitted(cs->fence, seq_no, user_fence); } _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
