Module: Mesa Branch: master Commit: df6349159443dc365705d2363c1f5daaa387508e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=df6349159443dc365705d2363c1f5daaa387508e
Author: Samuel Pitoiset <[email protected]> Date: Mon Sep 28 17:16:40 2020 +0200 radv/aco: lower IO for all stages outside of ACO Lowering IO for VS, TCS, TES and GS still have to be done for LLVM. No fossils-db change on NAVI10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6897> --- src/amd/compiler/aco_instruction_selection_setup.cpp | 10 ---------- src/amd/vulkan/radv_pipeline.c | 5 ++--- src/amd/vulkan/radv_shader.c | 18 ++++++++++++++---- src/amd/vulkan/radv_shader.h | 2 +- 4 files changed, 17 insertions(+), 18 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 367524c5e38..3ed0dbc286a 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -375,13 +375,6 @@ RegClass get_reg_class(isel_context *ctx, RegType type, unsigned components, uns return RegClass::get(type, components * bitsize / 8u); } -int -type_size(const struct glsl_type *type, bool bindless) -{ - // TODO: don't we need type->std430_base_alignment() here? - return glsl_count_attribute_slots(type, false); -} - bool mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size, @@ -653,9 +646,6 @@ setup_nir(isel_context *ctx, nir_shader *nir) lower_to_scalar = true; lower_pack = true; } - if (nir->info.stage != MESA_SHADER_COMPUTE && - nir->info.stage != MESA_SHADER_FRAGMENT) - nir_lower_io(nir, nir_var_shader_in | nir_var_shader_out, type_size, (nir_lower_io_options)0); lower_to_scalar |= nir_opt_shrink_vectors(nir); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 600ce8f478e..d67d9eba545 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2973,12 +2973,11 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline, nir_lower_non_uniform_image_access); } NIR_PASS_V(nir[i], nir_lower_memory_model); + + radv_lower_io(device, nir[i]); } } - if (nir[MESA_SHADER_FRAGMENT]) - radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]); - for (int i = 0; i < MESA_SHADER_STAGES; ++i) { if (radv_can_dump_shader(device, modules[i], false)) nir_print_shader(nir[i], stderr); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 88a50414334..d464daa473c 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -755,11 +755,21 @@ lower_view_index(nir_shader *nir) } void -radv_lower_fs_io(nir_shader *nir) +radv_lower_io(struct radv_device *device, nir_shader *nir) { - NIR_PASS_V(nir, lower_view_index); - nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, - MESA_SHADER_FRAGMENT); + if (nir->info.stage == MESA_SHADER_COMPUTE) + return; + + /* TODO: Lower IO for all stages with LLVM. */ + if (nir->info.stage != MESA_SHADER_FRAGMENT && + radv_use_llvm_for_stage(device, nir->info.stage)) + return; + + if (nir->info.stage == MESA_SHADER_FRAGMENT) { + NIR_PASS_V(nir, lower_view_index); + nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, + MESA_SHADER_FRAGMENT); + } NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size_vec4, 0); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 59497891ffd..f8b5893cb77 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -634,6 +634,6 @@ get_tcs_num_patches(unsigned tcs_num_input_vertices, } void -radv_lower_fs_io(nir_shader *nir); +radv_lower_io(struct radv_device *device, nir_shader *nir); #endif _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
