Module: Mesa Branch: master Commit: a38a497b86cffa9a67f95cb4a39c77642a2ef0a9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a38a497b86cffa9a67f95cb4a39c77642a2ef0a9
Author: Daniel Schürmann <[email protected]> Date: Fri Sep 18 00:02:21 2020 +0100 aco: use p_create_vector for nir_op_pack_half_2x16 This enables the use of SDWA if possible Totals from 2218 (1.62% of 136546) affected shaders (RAVEN): VGPRs: 68508 -> 68516 (+0.01%) CodeSize: 4897024 -> 4881068 (-0.33%); split: -0.33%, +0.00% MaxWaves: 18992 -> 18990 (-0.01%) Instrs: 946942 -> 939161 (-0.82%); split: -0.82%, +0.00% Cycles: 8737668 -> 8705704 (-0.37%); split: -0.37%, +0.00% VMEM: 1155362 -> 1145245 (-0.88%); split: +0.00%, -0.88% SMEM: 170435 -> 170165 (-0.16%); split: +0.01%, -0.16% VClause: 18426 -> 18425 (-0.01%) SClause: 41376 -> 41375 (-0.00%) Copies: 59813 -> 59787 (-0.04%); split: -0.15%, +0.10% PreVGPRs: 56126 -> 56136 (+0.02%) Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6777> --- src/amd/compiler/aco_instruction_selection.cpp | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index cbae52309bd..e75110704c6 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2618,14 +2618,9 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) if (0 && (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)) { bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1); } else { - src0 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src0); - src1 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src1); - if (ctx->program->chip_class >= GFX10) { - /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */ - bld.vop3(aco_opcode::v_pack_b32_f16, Definition(dst), src0, src1); - } else { - bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst), src0, src1); - } + src0 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v2b), src0); + src1 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v2b), src1); + bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1); } } else { isel_err(&instr->instr, "Unimplemented NIR instr bit size"); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
