Module: Mesa
Branch: master
Commit: ee1d30ab8a9e53bca2a146e175a8aa6a28ec02bd
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee1d30ab8a9e53bca2a146e175a8aa6a28ec02bd

Author: Samuel Pitoiset <[email protected]>
Date:   Wed May  6 11:42:43 2020 +0200

radv: flush CB before and after FMASK_DECOMPRESS or DCC_DECOMPRESS

According to RadeonSI and AMDVLK, it seems required to flush CB
before and after FMASK_DECOMPRESS or DCC_DECOMPRESS.

This shouldn't much affect performance because the driver already
flushes CB after these operations (including FCE too).

Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4913>

---

 src/amd/vulkan/radv_meta_fast_clear.c | 35 +++++++++++++++++++++++++++--------
 1 file changed, 27 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c 
b/src/amd/vulkan/radv_meta_fast_clear.c
index d60e8626261..9e587c3d7c0 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -585,7 +585,7 @@ static void
 radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer,
                               struct radv_image *image,
                               const VkImageSubresourceRange *range,
-                              int level, int layer)
+                              int level, int layer, bool flush_cb)
 {
        struct radv_device *device = cmd_buffer->device;
        struct radv_image_view iview;
@@ -638,10 +638,15 @@ radv_process_color_image_layer(struct radv_cmd_buffer 
*cmd_buffer,
        radv_cmd_buffer_set_subpass(cmd_buffer,
                                    &cmd_buffer->state.pass->subpasses[0]);
 
+       if (flush_cb)
+               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+                                               
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+
        radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
 
-       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
-                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+       if (flush_cb)
+               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+                                               
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
 
        radv_cmd_buffer_end_render_pass(cmd_buffer);
 
@@ -655,27 +660,37 @@ radv_process_color_image(struct radv_cmd_buffer 
*cmd_buffer,
                         const VkImageSubresourceRange *subresourceRange,
                         bool decompress_dcc)
 {
+       struct radv_device *device = cmd_buffer->device;
        struct radv_meta_saved_state saved_state;
+       bool flush_cb = false;
        VkPipeline *pipeline;
 
        if (decompress_dcc && radv_dcc_enabled(image, 
subresourceRange->baseMipLevel)) {
-               pipeline = 
&cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
+               pipeline = 
&device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
        } else if (radv_image_has_fmask(image) && !image->tc_compatible_cmask) {
-               pipeline = 
&cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
+               pipeline = 
&device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
        } else {
-               pipeline = 
&cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
+               pipeline = 
&device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
        }
 
        if (!*pipeline) {
                VkResult ret;
 
-               ret = 
radv_device_init_meta_fast_clear_flush_state_internal(cmd_buffer->device);
+               ret = 
radv_device_init_meta_fast_clear_flush_state_internal(device);
                if (ret != VK_SUCCESS) {
                        cmd_buffer->record_result = ret;
                        return;
                }
        }
 
+       if (pipeline == 
&device->meta_state.fast_clear_flush.dcc_decompress_pipeline ||
+           pipeline == 
&device->meta_state.fast_clear_flush.fmask_decompress_pipeline) {
+               /* Flushing CB is required before and after DCC_DECOMPRESS or
+                * FMASK_DECOMPRESS.
+                */
+               flush_cb = true;
+       }
+
        radv_meta_save(&saved_state, cmd_buffer,
                       RADV_META_SAVE_GRAPHICS_PIPELINE |
                       RADV_META_SAVE_PASS);
@@ -714,10 +729,14 @@ radv_process_color_image(struct radv_cmd_buffer 
*cmd_buffer,
 
                for (uint32_t s = 0; s < radv_get_layerCount(image, 
subresourceRange); s++) {
                        radv_process_color_image_layer(cmd_buffer, image,
-                                                      subresourceRange, l, s);
+                                                      subresourceRange, l, s,
+                                                      flush_cb);
                }
        }
 
+       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+
        radv_meta_restore(&saved_state, cmd_buffer);
 }
 

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