Module: Mesa Branch: master Commit: a1d2b215f10dc5fe9dfa2d027b6c07dd8d6849f7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1d2b215f10dc5fe9dfa2d027b6c07dd8d6849f7
Author: Connor Abbott <[email protected]> Date: Thu Oct 29 11:08:08 2020 +0100 tu: Use freedreno_dev_info Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7385> --- src/freedreno/vulkan/tu_clear_blit.c | 6 ++++-- src/freedreno/vulkan/tu_cmd_buffer.c | 24 ++++++++++++------------ src/freedreno/vulkan/tu_device.c | 21 +-------------------- src/freedreno/vulkan/tu_nir_lower_multiview.c | 2 +- src/freedreno/vulkan/tu_pass.c | 11 ++++++----- src/freedreno/vulkan/tu_pipeline.c | 2 +- src/freedreno/vulkan/tu_private.h | 15 ++------------- src/freedreno/vulkan/tu_util.c | 9 +++++---- 8 files changed, 32 insertions(+), 58 deletions(-) diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index 3508c200073..a0f692444f8 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -2418,6 +2418,7 @@ tu_store_gmem_attachment(struct tu_cmd_buffer *cmd, uint32_t a, uint32_t gmem_a) { + struct tu_physical_device *phys_dev = cmd->device->physical_device; const VkRect2D *render_area = &cmd->state.render_area; struct tu_render_pass_attachment *dst = &cmd->state.pass->attachments[a]; struct tu_image_view *iview = cmd->state.framebuffer->attachments[a].attachment; @@ -2439,8 +2440,9 @@ tu_store_gmem_attachment(struct tu_cmd_buffer *cmd, y2 != iview->extent.height || iview->need_y2_align; bool unaligned = - x1 % GMEM_ALIGN_W || (x2 % GMEM_ALIGN_W && x2 != iview->extent.width) || - y1 % GMEM_ALIGN_H || (y2 % GMEM_ALIGN_H && need_y2_align); + x1 % phys_dev->info.gmem_align_w || + (x2 % phys_dev->info.gmem_align_w && x2 != iview->extent.width) || + y1 % phys_dev->info.gmem_align_h || (y2 % phys_dev->info.gmem_align_h && need_y2_align); /* use fast path when render area is aligned, except for unsupported resolve cases */ if (!unaligned && (a == gmem_a || blit_can_resolve(dst->format))) { diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index c8e044edfdc..8d85422d24b 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -160,8 +160,8 @@ tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer, tu_cs_emit_regs(cs, A6XX_RB_CCU_CNTL(.offset = ccu_state == TU_CMD_CCU_GMEM ? - phys_dev->ccu_offset_gmem : - phys_dev->ccu_offset_bypass, + phys_dev->info.a6xx.ccu_offset_gmem : + phys_dev->info.a6xx.ccu_offset_bypass, .gmem = ccu_state == TU_CMD_CCU_GMEM)); cmd_buffer->state.ccu_state = ccu_state; } @@ -369,7 +369,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd, static void tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align) { - + struct tu_physical_device *phys_dev = cmd->device->physical_device; const VkRect2D *render_area = &cmd->state.render_area; /* Avoid assertion fails with an empty render area at (0, 0) where the @@ -388,10 +388,10 @@ tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align) uint32_t y2 = y1 + render_area->extent.height - 1; if (align) { - x1 = x1 & ~(GMEM_ALIGN_W - 1); - y1 = y1 & ~(GMEM_ALIGN_H - 1); - x2 = ALIGN_POT(x2 + 1, GMEM_ALIGN_W) - 1; - y2 = ALIGN_POT(y2 + 1, GMEM_ALIGN_H) - 1; + x1 = x1 & ~(phys_dev->info.gmem_align_w - 1); + y1 = y1 & ~(phys_dev->info.gmem_align_h - 1); + x2 = ALIGN_POT(x2 + 1, phys_dev->info.gmem_align_w) - 1; + y2 = ALIGN_POT(y2 + 1, phys_dev->info.gmem_align_h) - 1; } tu_cs_emit_regs(cs, @@ -729,7 +729,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) ~(TU_CMD_FLAG_WAIT_FOR_IDLE | TU_CMD_FLAG_CACHE_INVALIDATE); tu_cs_emit_regs(cs, - A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass)); + A6XX_RB_CCU_CNTL(.offset = phys_dev->info.a6xx.ccu_offset_bypass)); cmd->state.ccu_state = TU_CMD_CCU_SYSMEM; tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8); @@ -939,10 +939,10 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs) update_vsc_pipe(cmd, cs); tu_cs_emit_regs(cs, - A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805)); + A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->info.a6xx.magic.PC_UNKNOWN_9805)); tu_cs_emit_regs(cs, - A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8)); + A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->info.a6xx.magic.SP_UNKNOWN_A0F8)); tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1); tu_cs_emit(cs, UNK_2C); @@ -1226,9 +1226,9 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_regs(cs, A6XX_VFD_MODE_CNTL(0)); - tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805)); + tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->info.a6xx.magic.PC_UNKNOWN_9805)); - tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8)); + tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->info.a6xx.magic.SP_UNKNOWN_A0F8)); tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); tu_cs_emit(cs, 0x1); diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c index c1eb9e8e838..3c834c62eca 100644 --- a/src/freedreno/vulkan/tu_device.c +++ b/src/freedreno/vulkan/tu_device.c @@ -80,29 +80,10 @@ tu_physical_device_init(struct tu_physical_device *device, switch (device->gpu_id) { case 615: case 618: - device->ccu_offset_gmem = 0x7c000; /* 0x7e000 in some cases? */ - device->ccu_offset_bypass = 0x10000; - device->tile_align_w = 32; - device->magic.PC_UNKNOWN_9805 = 0x0; - device->magic.SP_UNKNOWN_A0F8 = 0x0; - device->supports_multiview_mask = false; /* TODO */ - break; case 630: case 640: - device->ccu_offset_gmem = 0xf8000; - device->ccu_offset_bypass = 0x20000; - device->tile_align_w = 32; - device->magic.PC_UNKNOWN_9805 = 0x1; - device->magic.SP_UNKNOWN_A0F8 = 0x1; - device->supports_multiview_mask = device->gpu_id != 630; - break; case 650: - device->ccu_offset_gmem = 0x114000; - device->ccu_offset_bypass = 0x30000; - device->tile_align_w = 96; - device->magic.PC_UNKNOWN_9805 = 0x2; - device->magic.SP_UNKNOWN_A0F8 = 0x2; - device->supports_multiview_mask = true; + freedreno_dev_info_init(&device->info, device->gpu_id); break; default: result = vk_startup_errorf(instance, VK_ERROR_INITIALIZATION_FAILED, diff --git a/src/freedreno/vulkan/tu_nir_lower_multiview.c b/src/freedreno/vulkan/tu_nir_lower_multiview.c index 80ec26e9bc4..95ac6b3a102 100644 --- a/src/freedreno/vulkan/tu_nir_lower_multiview.c +++ b/src/freedreno/vulkan/tu_nir_lower_multiview.c @@ -78,7 +78,7 @@ tu_nir_lower_multiview(nir_shader *nir, uint32_t mask, bool *multi_pos_output, bool progress = false; - if (!dev->physical_device->supports_multiview_mask) + if (!dev->physical_device->info.a6xx.supports_multiview_mask) NIR_PASS(progress, nir, lower_multiview_mask, &mask); unsigned num_views = util_logbase2(mask) + 1; diff --git a/src/freedreno/vulkan/tu_pass.c b/src/freedreno/vulkan/tu_pass.c index c31c830a330..7e6a21fcede 100644 --- a/src/freedreno/vulkan/tu_pass.c +++ b/src/freedreno/vulkan/tu_pass.c @@ -343,8 +343,8 @@ tu_render_pass_gmem_config(struct tu_render_pass *pass, const struct tu_physical_device *phys_dev) { uint32_t block_align_shift = 3; /* log2(gmem_align/(tile_align_w*tile_align_h)) */ - uint32_t tile_align_w = phys_dev->tile_align_w; - uint32_t gmem_align = (1 << block_align_shift) * tile_align_w * TILE_ALIGN_H; + uint32_t tile_align_w = phys_dev->info.tile_align_w; + uint32_t gmem_align = (1 << block_align_shift) * tile_align_w * phys_dev->info.tile_align_h; /* calculate total bytes per pixel */ uint32_t cpp_total = 0; @@ -386,7 +386,7 @@ tu_render_pass_gmem_config(struct tu_render_pass *pass, * result: nblocks = {12, 52}, pixels = 196608 * optimal: nblocks = {13, 51}, pixels = 208896 */ - uint32_t gmem_blocks = phys_dev->ccu_offset_gmem / gmem_align; + uint32_t gmem_blocks = phys_dev->info.a6xx.ccu_offset_gmem / gmem_align; uint32_t offset = 0, pixels = ~0u, i; for (i = 0; i < pass->attachment_count; i++) { struct tu_render_pass_attachment *att = &pass->attachments[i]; @@ -664,6 +664,7 @@ tu_GetRenderAreaGranularity(VkDevice _device, VkRenderPass renderPass, VkExtent2D *pGranularity) { - pGranularity->width = GMEM_ALIGN_W; - pGranularity->height = GMEM_ALIGN_H; + TU_FROM_HANDLE(tu_device, device, _device); + pGranularity->width = device->physical_device->info.gmem_align_w; + pGranularity->height = device->physical_device->info.gmem_align_h; } diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index a85562791e2..6fe57972eab 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -1482,7 +1482,7 @@ tu6_emit_program(struct tu_cs *cs, tu_cs_emit(cs, multiview_cntl); if (multiview_cntl && - builder->device->physical_device->supports_multiview_mask) { + builder->device->physical_device->info.a6xx.supports_multiview_mask) { tu_cs_emit_pkt4(cs, REG_A6XX_PC_MULTIVIEW_MASK, 1); tu_cs_emit(cs, builder->multiview_mask); } diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h index ca2d863c238..0b18d8e6067 100644 --- a/src/freedreno/vulkan/tu_private.h +++ b/src/freedreno/vulkan/tu_private.h @@ -63,6 +63,7 @@ #include "adreno_pm4.xml.h" #include "a6xx.xml.h" #include "fdl/freedreno_layout.h" +#include "common/freedreno_dev_info.h" #include "tu_descriptor_set.h" #include "tu_extensions.h" @@ -196,20 +197,8 @@ struct tu_physical_device unsigned gpu_id; uint32_t gmem_size; uint64_t gmem_base; - uint32_t ccu_offset_gmem; - uint32_t ccu_offset_bypass; - /* alignment for size of tiles */ - uint32_t tile_align_w; -#define TILE_ALIGN_H 16 - /* gmem store/load granularity */ -#define GMEM_ALIGN_W 16 -#define GMEM_ALIGN_H 4 - bool supports_multiview_mask; - struct { - uint32_t PC_UNKNOWN_9805; - uint32_t SP_UNKNOWN_A0F8; - } magic; + struct freedreno_dev_info info; int msm_major_version; int msm_minor_version; diff --git a/src/freedreno/vulkan/tu_util.c b/src/freedreno/vulkan/tu_util.c index f9ca940a17f..07fc149c0d3 100644 --- a/src/freedreno/vulkan/tu_util.c +++ b/src/freedreno/vulkan/tu_util.c @@ -84,6 +84,7 @@ tu_tiling_config_update_tile_layout(struct tu_framebuffer *fb, const struct tu_render_pass *pass) { const uint32_t tile_align_w = pass->tile_align_w; + const uint32_t tile_align_h = dev->physical_device->info.tile_align_h; const uint32_t max_tile_width = 1024; /* start from 1 tile */ @@ -93,7 +94,7 @@ tu_tiling_config_update_tile_layout(struct tu_framebuffer *fb, }; fb->tile0 = (VkExtent2D) { .width = util_align_npot(fb->width, tile_align_w), - .height = align(fb->height, TILE_ALIGN_H), + .height = align(fb->height, tile_align_h), }; if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) { @@ -101,7 +102,7 @@ tu_tiling_config_update_tile_layout(struct tu_framebuffer *fb, fb->tile_count.width = 2; fb->tile_count.height = 2; fb->tile0.width = util_align_npot(DIV_ROUND_UP(fb->width, 2), tile_align_w); - fb->tile0.height = align(DIV_ROUND_UP(fb->height, 2), TILE_ALIGN_H); + fb->tile0.height = align(DIV_ROUND_UP(fb->height, 2), tile_align_h); } /* do not exceed max tile width */ @@ -125,10 +126,10 @@ tu_tiling_config_update_tile_layout(struct tu_framebuffer *fb, util_align_npot(DIV_ROUND_UP(fb->width, fb->tile_count.width), tile_align_w); } else { /* if this assert fails then layout is impossible.. */ - assert(fb->tile0.height > TILE_ALIGN_H); + assert(fb->tile0.height > tile_align_h); fb->tile_count.height++; fb->tile0.height = - align(DIV_ROUND_UP(fb->height, fb->tile_count.height), TILE_ALIGN_H); + align(DIV_ROUND_UP(fb->height, fb->tile_count.height), tile_align_h); } } } _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
