Module: Mesa
Branch: master
Commit: c82d7be193474f590ab6d9381a39deb8943d787b
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c82d7be193474f590ab6d9381a39deb8943d787b

Author: Connor Abbott <[email protected]>
Date:   Fri Oct 23 13:46:47 2020 +0200

ir3: Expand cat6 a6xx opcode field

Turns out the low bit of pad3 is actually the high bit of the opcode.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7386>

---

 src/freedreno/ir3/instr-a3xx.h | 14 +++++++-------
 src/freedreno/ir3/ir3.c        |  8 ++++----
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h
index 1b0f7089c18..798013e1295 100644
--- a/src/freedreno/ir3/instr-a3xx.h
+++ b/src/freedreno/ir3/instr-a3xx.h
@@ -888,23 +888,23 @@ typedef enum {
 /**
  * For atomic ops (which return a value):
  *
- *    pad1=1, pad3=c, pad5=3
+ *    pad1=1, pad3=6, pad5=3
  *    src1    - vecN offset/coords
  *    src2.x  - is actually dest register
  *    src2.y  - is 'data' except for cmpxchg where src2.y is 'compare'
  *              and src2.z is 'data'
  *
  * For stib (which does not return a value):
- *    pad1=0, pad3=c, pad5=2
+ *    pad1=0, pad3=6, pad5=2
  *    src1    - vecN offset/coords
  *    src2    - value to store
  *
  * For ldib:
- *    pad1=1, pad3=c, pad5=2
+ *    pad1=1, pad3=6, pad5=2
  *    src1    - vecN offset/coords
  *
  * for ldc (load from UBO using descriptor):
- *    pad1=0, pad3=8, pad5=2
+ *    pad1=0, pad3=4, pad5=2
  *
  * pad2 and pad5 are only observed to be 0.
  */
@@ -917,8 +917,8 @@ typedef struct PACKED {
        uint32_t d        : 2;
        uint32_t typed    : 1;
        uint32_t type_size : 2;
-       uint32_t opc      : 5;
-       uint32_t pad3     : 5;
+       uint32_t opc      : 6;
+       uint32_t pad3     : 4;
        uint32_t src1     : 8;  /* coordinate/offset */
 
        /* dword1: */
@@ -1011,7 +1011,7 @@ static inline bool is_cat6_legacy(instr_t *instr, 
unsigned gpu_id)
         * cmdstream traces I have indicates that the pad bit is zero
         * in all cases.  So we can use this to detect new encoding:
         */
-       if ((cat6->pad3 & 0x8) && (cat6->pad5 & 0x2)) {
+       if ((cat6->pad3 & 0x4) && (cat6->pad5 & 0x2)) {
                ir3_assert(gpu_id >= 600);
                ir3_assert(instr->cat6.opc == 0);
                return false;
diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c
index 2f2612d40c6..8966e7afecc 100644
--- a/src/freedreno/ir3/ir3.c
+++ b/src/freedreno/ir3/ir3.c
@@ -599,23 +599,23 @@ static int emit_cat6_a6xx(struct ir3_instruction *instr, 
void *ptr,
        case OPC_ATOMIC_OR:
        case OPC_ATOMIC_XOR:
                cat6->pad1 = 0x1;
-               cat6->pad3 = 0xc;
+               cat6->pad3 = 0x6;
                cat6->pad5 = 0x3;
                break;
        case OPC_STIB:
                cat6->pad1 = 0x0;
-               cat6->pad3 = 0xc;
+               cat6->pad3 = 0x6;
                cat6->pad5 = 0x2;
                break;
        case OPC_LDIB:
        case OPC_RESINFO:
                cat6->pad1 = 0x1;
-               cat6->pad3 = 0xc;
+               cat6->pad3 = 0x6;
                cat6->pad5 = 0x2;
                break;
        case OPC_LDC:
                cat6->pad1 = 0x0;
-               cat6->pad3 = 0x8;
+               cat6->pad3 = 0x4;
                cat6->pad5 = 0x2;
                break;
        default:

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