Module: Mesa Branch: master Commit: f7f6e9ad56df4f41a4dd9f4344b298ae17f25ad1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7f6e9ad56df4f41a4dd9f4344b298ae17f25ad1
Author: Samuel Pitoiset <[email protected]> Date: Wed Dec 9 17:28:40 2020 +0100 radv: always clear the SR0/SR1 bits of the HTILE buffer To make sure the stencil compare state is properly initialized and cleared when the driver performs a fast depth clear. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039> --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_meta_clear.c | 2 +- src/amd/vulkan/radv_meta_resolve_cs.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 6d8dc755b40..3d61a912889 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6000,7 +6000,7 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS); VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT; struct radv_cmd_state *state = &cmd_buffer->state; - uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f; + uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff3ff : 0xfffc000f; VkClearDepthStencilValue value = {0}; struct radv_barrier_data barrier = {0}; diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index ec5435ca04c..8b95fdb15a7 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -953,7 +953,7 @@ radv_get_htile_fast_clear_value(const struct radv_image *image, if (!image->planes[0].surface.has_stencil) { clear_value = value.depth ? 0xfffffff0 : 0; } else { - clear_value = value.depth ? 0xfffc0000 : 0; + clear_value = value.depth ? 0xfffc00f0 : 0xf0; } return clear_value; diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 0706281b8fd..41bfa4ff18b 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -998,7 +998,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer, * buffer if it's resolved, otherwise this * might break if the stencil has been cleared. */ - clear_value = 0xfffff30f; + clear_value = 0xfffff3ff; } cmd_buffer->state.flush_bits |= _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
