Module: Mesa Branch: master Commit: f961cf2047d6a1a1cd3f15b20821ea4aa0aa90be URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f961cf2047d6a1a1cd3f15b20821ea4aa0aa90be
Author: Nanley Chery <[email protected]> Date: Mon Dec 14 15:03:26 2020 -0800 blorp: Assert 8x4 alignment for a HiZ op on Gen8-9 On BDW and SKL, assert that render target dimensions are 8x4-aligned when performing HiZ ambiguates on LOD1+. Testing indicates that the assertion should hold in order to achieve consistent/correct ambiguate operations on gen9. v2. Account for the relaxed restrictions on ICL+. (Ken) Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3788 Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8853> --- src/intel/blorp/blorp.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index fe2027fae19..c6f3f1b41d8 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -323,6 +323,8 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf, uint32_t level, uint32_t start_layer, uint32_t num_layers, enum isl_aux_op op) { + const struct gen_device_info *devinfo = batch->blorp->isl_dev->info; + struct blorp_params params; blorp_params_init(¶ms); @@ -386,6 +388,41 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf, /* TODO: What about MSAA? */ params.depth.surf.logical_level0_px.width = params.x1; params.depth.surf.logical_level0_px.height = params.y1; + } else if (devinfo->gen >= 8 && devinfo->gen <= 9 && + op == ISL_AUX_OP_AMBIGUATE) { + /* On some platforms, it's not enough to just adjust the clear + * rectangle when the LOD is greater than 0. + * + * From the BDW and SKL PRMs, Vol 7, "Optimized Hierarchical Depth + * Buffer Resolve": + * + * The following is required when performing a hierarchical depth + * buffer resolve: + * + * - A rectangle primitive covering the full render target must be + * programmed on Xmin, Ymin, Xmax, and Ymax in the + * 3DSTATE_WM_HZ_OP command. + * + * - The rectangle primitive size must be aligned to 8x4 pixels. + * + * And from the Clear Rectangle programming note in 3DSTATE_WM_HZ_OP + * (Vol 2a): + * + * Hence the max values must be less than or equal to: ( Surface + * Width » LOD ) and ( Surface Height » LOD ) for X Max and Y Max + * respectively. + * + * This means that the extent of the LOD must be naturally + * 8x4-aligned after minification of the base LOD. Since the base LOD + * dimensions affect the placement of smaller LODs, it's not trivial + * (nor possible, at times) to satisfy the requirement by adjusting + * the base LOD extent. Just assert that the caller is accessing an + * LOD that satisfies this requirement. + */ + assert(minify(params.depth.surf.logical_level0_px.width, + params.depth.view.base_level) == params.x1); + assert(minify(params.depth.surf.logical_level0_px.height, + params.depth.view.base_level) == params.y1); } params.dst.surf.samples = params.depth.surf.samples; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
