Module: Mesa Branch: master Commit: 1d0295ea2ca92c10e627841d8985fbce26883243 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d0295ea2ca92c10e627841d8985fbce26883243
Author: Anuj Phogat <[email protected]> Date: Tue Mar 9 14:27:06 2021 -0800 intel: Simplify version checks involving haswell Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608> --- src/intel/blorp/blorp_genX_exec.h | 2 +- src/intel/common/mi_builder.h | 40 +++++++++++++-------------- src/intel/common/tests/mi_builder_test.cpp | 8 +++--- src/intel/genxml/gen_macros.h | 4 +-- src/intel/isl/isl_emit_depth_stencil.c | 2 +- src/intel/isl/isl_surface_state.c | 6 ++-- src/intel/vulkan/gen7_cmd_buffer.c | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 34 +++++++++++------------ src/intel/vulkan/genX_pipeline.c | 4 +-- src/intel/vulkan/genX_query.c | 2 +- src/mesa/drivers/dri/i965/genX_pipe_control.c | 2 +- src/mesa/drivers/dri/i965/genX_state_upload.c | 18 ++++++------ 12 files changed, 62 insertions(+), 62 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 416627bcfe2..c1af5d6acef 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -227,7 +227,7 @@ emit_urb_config(struct blorp_batch *batch, false, false, entry_size, entries, start, deref_block_size, &constrained); -#if GEN_GEN == 7 && GEN_VERSIONx10 != 75 +#if GEN_VERSIONx10 == 70 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: * * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall diff --git a/src/intel/common/mi_builder.h b/src/intel/common/mi_builder.h index 901a335949e..e3d9b62df6a 100644 --- a/src/intel/common/mi_builder.h +++ b/src/intel/common/mi_builder.h @@ -95,7 +95,7 @@ struct mi_value { uint32_t reg; }; -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 bool invert; #endif }; @@ -130,7 +130,7 @@ mi_adjust_reg_num(uint32_t reg) struct mi_builder { __gen_user_data *user_data; -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 uint32_t gprs; uint8_t gpr_refs[MI_BUILDER_NUM_ALLOC_GPRS]; @@ -145,7 +145,7 @@ mi_builder_init(struct mi_builder *b, __gen_user_data *user_data) memset(b, 0, sizeof(*b)); b->user_data = user_data; -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 b->gprs = 0; b->num_math_dwords = 0; #endif @@ -154,7 +154,7 @@ mi_builder_init(struct mi_builder *b, __gen_user_data *user_data) static inline void mi_builder_flush_math(struct mi_builder *b) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (b->num_math_dwords == 0) return; @@ -172,7 +172,7 @@ mi_builder_flush_math(struct mi_builder *b) /* The actual hardware limit on GPRs */ #define _MI_BUILDER_NUM_HW_GPRS 16 -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 static inline bool mi_value_is_reg(struct mi_value val) @@ -221,7 +221,7 @@ mi_new_gpr(struct mi_builder *b) .reg = _MI_BUILDER_GPR_BASE + gpr * 8, }; } -#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */ +#endif /* GEN_VERSIONx10 >= 75 */ /** Take a reference to a mi_value * @@ -236,7 +236,7 @@ mi_new_gpr(struct mi_builder *b) static inline struct mi_value mi_value_ref(struct mi_builder *b, struct mi_value val) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (_mi_value_is_allocated_gpr(val)) { unsigned gpr = _mi_value_as_gpr(val); assert(gpr < MI_BUILDER_NUM_ALLOC_GPRS); @@ -244,7 +244,7 @@ mi_value_ref(struct mi_builder *b, struct mi_value val) assert(b->gpr_refs[gpr] < UINT8_MAX); b->gpr_refs[gpr]++; } -#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */ +#endif /* GEN_VERSIONx10 >= 75 */ return val; } @@ -256,7 +256,7 @@ mi_value_ref(struct mi_builder *b, struct mi_value val) static inline void mi_value_unref(struct mi_builder *b, struct mi_value val) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (_mi_value_is_allocated_gpr(val)) { unsigned gpr = _mi_value_as_gpr(val); assert(gpr < MI_BUILDER_NUM_ALLOC_GPRS); @@ -265,7 +265,7 @@ mi_value_unref(struct mi_builder *b, struct mi_value val) if (--b->gpr_refs[gpr] == 0) b->gprs &= ~(1u << gpr); } -#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */ +#endif /* GEN_VERSIONx10 >= 75 */ } static inline struct mi_value @@ -284,7 +284,7 @@ mi_reg32(uint32_t reg) .type = MI_VALUE_TYPE_REG32, .reg = reg, }; -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 assert(!_mi_value_is_allocated_gpr(val)); #endif return val; @@ -297,7 +297,7 @@ mi_reg64(uint32_t reg) .type = MI_VALUE_TYPE_REG64, .reg = reg, }; -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 assert(!_mi_value_is_allocated_gpr(val)); #endif return val; @@ -360,7 +360,7 @@ static inline void _mi_copy_no_unref(struct mi_builder *b, struct mi_value dst, struct mi_value src) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 /* TODO: We could handle src.invert by emitting a bit of math if we really * wanted to. */ @@ -506,7 +506,7 @@ _mi_copy_no_unref(struct mi_builder *b, case MI_VALUE_TYPE_REG32: case MI_VALUE_TYPE_REG64: -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (src.reg != dst.reg) { mi_builder_emit(b, GENX(MI_LOAD_REGISTER_REG), lrr) { struct mi_reg_num reg = mi_adjust_reg_num(src.reg); @@ -536,7 +536,7 @@ _mi_copy_no_unref(struct mi_builder *b, } } -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 static inline struct mi_value mi_resolve_invert(struct mi_builder *b, struct mi_value src); #endif @@ -552,7 +552,7 @@ mi_resolve_invert(struct mi_builder *b, struct mi_value src); static inline void mi_store(struct mi_builder *b, struct mi_value dst, struct mi_value src) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 src = mi_resolve_invert(b, src); #endif _mi_copy_no_unref(b, dst, src); @@ -564,7 +564,7 @@ static inline void mi_memset(struct mi_builder *b, __gen_address_type dst, uint32_t value, uint32_t size) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 assert(b->num_math_dwords == 0); #endif @@ -582,7 +582,7 @@ static inline void mi_memcpy(struct mi_builder *b, __gen_address_type dst, __gen_address_type src, uint32_t size) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 assert(b->num_math_dwords == 0); #endif @@ -592,7 +592,7 @@ mi_memcpy(struct mi_builder *b, __gen_address_type dst, for (uint32_t i = 0; i < size; i += 4) { struct mi_value dst_val = mi_mem32(__gen_address_offset(dst, i)); struct mi_value src_val = mi_mem32(__gen_address_offset(src, i)); -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 mi_store(b, dst_val, src_val); #else /* IVB does not have a general purpose register for command streamer @@ -609,7 +609,7 @@ mi_memcpy(struct mi_builder *b, __gen_address_type dst, * MI_MATH Section. Only available on Haswell+ */ -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 /** * Perform a predicated store (assuming the condition is already loaded diff --git a/src/intel/common/tests/mi_builder_test.cpp b/src/intel/common/tests/mi_builder_test.cpp index 90385b79901..0d6d5a072d1 100644 --- a/src/intel/common/tests/mi_builder_test.cpp +++ b/src/intel/common/tests/mi_builder_test.cpp @@ -55,7 +55,7 @@ __gen_address_offset(address addr, uint64_t offset) return addr; } -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 #define RSVD_TEMP_REG 0x2678 /* MI_ALU_REG15 */ #else #define RSVD_TEMP_REG 0x2430 /* GEN7_3DPRIM_START_VERTEX */ @@ -412,7 +412,7 @@ TEST_F(mi_builder_test, imm_mem) } /* mem -> mem copies are only supported on HSW+ */ -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 TEST_F(mi_builder_test, mem_mem) { const uint64_t value = 0x0123456789abcdef; @@ -532,7 +532,7 @@ TEST_F(mi_builder_test, memcpy) } /* Start of MI_MATH section */ -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 #define EXPECT_EQ_IMM(x, imm) EXPECT_EQ(x, mi_value_to_u64(imm)) @@ -953,7 +953,7 @@ TEST_F(mi_builder_test, store_if) EXPECT_EQ(*(uint32_t *)(output + 12), (uint32_t)canary); } -#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */ +#endif /* GEN_VERSIONx10 >= 75 */ #if GEN_VERSIONx10 >= 125 diff --git a/src/intel/genxml/gen_macros.h b/src/intel/genxml/gen_macros.h index e5e538941db..838b28d20be 100644 --- a/src/intel/genxml/gen_macros.h +++ b/src/intel/genxml/gen_macros.h @@ -31,7 +31,7 @@ * * You can do pseudo-runtime checks in your function such as * - * if (GEN_GEN > 8 || GEN_VERSIONx10 == 75) { + * if (GEN_VERSIONx10 == 75) { * // Do something * } * @@ -41,7 +41,7 @@ * For places where you really do have a compile-time conflict, you can * use preprocessor logic: * - * #if (GEN_GEN > 8 || GEN_VERSIONx10 == 75) + * #if (GEN_VERSIONx10 == 75) * // Do something * #endif * diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index eee61694169..3bb7eec37a1 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -169,7 +169,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, sb.StencilCompressionEnable = info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS; sb.ControlSurfaceEnable = sb.StencilCompressionEnable; -#elif GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#elif GEN_VERSIONx10 >= 75 sb.StencilBufferEnable = true; #endif sb.SurfaceBaseAddress = info->stencil_address; diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index c425a4fd50a..1fcd24ef9f6 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -363,7 +363,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * * This restriction appears to exist only on Ivy Bridge. */ - if (GEN_GEN == 7 && GEN_VERSIONx10 != 75 && !ISL_DEV_IS_BAYTRAIL(dev) && + if (GEN_VERSIONx10 == 70 && !ISL_DEV_IS_BAYTRAIL(dev) && (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) && info->surf->samples > 1) assert(info->view->base_array_layer == 0); @@ -529,7 +529,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #endif -#if (GEN_GEN >= 8 || GEN_VERSIONx10 == 75) +#if (GEN_VERSIONx10 >= 75) if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle)); @@ -917,7 +917,7 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, s.MOCS = info->mocs; #endif -#if (GEN_GEN >= 8 || GEN_VERSIONx10 == 75) +#if (GEN_VERSIONx10 >= 75) s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r; s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g; s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b; diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c index deab2d09123..2e8cf5b8177 100644 --- a/src/intel/vulkan/gen7_cmd_buffer.c +++ b/src/intel/vulkan/gen7_cmd_buffer.c @@ -33,7 +33,7 @@ #include "genxml/gen_macros.h" #include "genxml/genX_pack.h" -#if GEN_GEN == 7 && GEN_VERSIONx10 != 75 +#if GEN_VERSIONx10 == 70 static int64_t clamp_int64(int64_t x, int64_t min, int64_t max) { diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 1a2474f40ed..e887aa8f97f 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -759,7 +759,7 @@ set_image_fast_clear_state(struct anv_cmd_buffer *cmd_buffer, /* This is only really practical on haswell and above because it requires * MI math in order to get it correct. */ -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 static void anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, @@ -840,7 +840,7 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer, mip.CompareOperation = COMPARE_SRCS_EQUAL; } } -#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */ +#endif /* GEN_VERSIONx10 >= 75 */ #if GEN_GEN <= 8 static void @@ -931,7 +931,7 @@ anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer, assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT); assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE); -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 anv_cmd_compute_resolve_predicate(cmd_buffer, image, aspect, 0, array_layer, resolve_op, fast_clear_supported); @@ -1000,7 +1000,7 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer, } else { anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { sdi.Address = addr; - if (GEN_GEN >= 8 || GEN_VERSIONx10 == 75) { + if (GEN_VERSIONx10 >= 75) { /* Pre-SKL, the dword containing the clear values also contains * other fields, so we need to initialize those fields to match the * values that would be in a color attachment. @@ -1682,7 +1682,7 @@ genX(BeginCommandBuffer)( cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS; } -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) { const VkCommandBufferInheritanceConditionalRenderingInfoEXT *conditional_rendering_info = vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT); @@ -1801,7 +1801,7 @@ genX(CmdExecuteCommands)( assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY); assert(!anv_batch_has_error(&secondary->batch)); -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (secondary->state.conditional_render_enabled) { if (!primary->state.conditional_render_enabled) { /* Secondary buffer is constructed as if it will be executed @@ -3053,7 +3053,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer, c.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0, false); #endif -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 /* The Skylake PRM contains the following restriction: * * "The driver must ensure The following case does not occur @@ -3076,7 +3076,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer, /* For Ivy Bridge, make sure we only set the first range (actual * push constants) */ - assert((GEN_GEN >= 8 || GEN_VERSIONx10 == 75) || i == 0); + assert((GEN_VERSIONx10 >= 75) || i == 0); c.ConstantBody.ReadLength[i + shift] = range->length; c.ConstantBody.Buffer[i + shift] = @@ -3780,7 +3780,7 @@ void genX(CmdDrawIndirectByteCountEXT)( uint32_t counterOffset, uint32_t vertexStride) { -#if GEN_VERSIONx10 == 75 || GEN_GEN >= 8 +#if GEN_VERSIONx10 >= 75 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, counter_buffer, counterBuffer); struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline; @@ -3838,7 +3838,7 @@ void genX(CmdDrawIndirectByteCountEXT)( } update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, SEQUENTIAL); -#endif /* GEN_VERSIONx10 == 75 || GEN_GEN >= 8 */ +#endif /* GEN_VERSIONx10 >= 75 */ } static void @@ -3855,7 +3855,7 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer, struct mi_value instance_count = mi_mem32(anv_address_add(addr, 4)); unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass); if (view_count > 1) { -#if GEN_VERSIONx10 == 75 || GEN_GEN >= 8 +#if GEN_VERSIONx10 >= 75 instance_count = mi_imul_imm(&b, instance_count, view_count); #else anv_finishme("Multiview + indirect draw requires MI_MATH; " @@ -3987,7 +3987,7 @@ prepare_for_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer, struct mi_value ret = mi_imm(0); if (conditional_render_enabled) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 ret = mi_new_gpr(b); mi_store(b, mi_value_ref(b, ret), mi_mem32(count_address)); #endif @@ -4032,7 +4032,7 @@ emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer, } } -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 static void emit_draw_count_predicate_with_conditional_render( struct anv_cmd_buffer *cmd_buffer, @@ -4094,7 +4094,7 @@ void genX(CmdDrawIndirectCount)( for (uint32_t i = 0; i < maxDrawCount; i++) { struct anv_address draw = anv_address_add(buffer->address, offset); -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (cmd_state->conditional_render_enabled) { emit_draw_count_predicate_with_conditional_render( cmd_buffer, &b, i, mi_value_ref(&b, max)); @@ -4165,7 +4165,7 @@ void genX(CmdDrawIndexedIndirectCount)( for (uint32_t i = 0; i < maxDrawCount; i++) { struct anv_address draw = anv_address_add(buffer->address, offset); -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 if (cmd_state->conditional_render_enabled) { emit_draw_count_predicate_with_conditional_render( cmd_buffer, &b, i, mi_value_ref(&b, max)); @@ -6071,7 +6071,7 @@ void genX(CmdEndRenderPass2)( void genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 struct mi_builder b; mi_builder_init(&b, &cmd_buffer->batch); @@ -6087,7 +6087,7 @@ genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer) #endif } -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 void genX(CmdBeginConditionalRenderingEXT)( VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index b2c0f3b581a..a31448b3afc 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -280,7 +280,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch, entry_size, entries, start, deref_block_size, &constrained); -#if GEN_GEN == 7 && GEN_VERSIONx10 != 75 +#if GEN_VERSIONx10 == 70 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: * * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall @@ -2451,7 +2451,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline, .ConstantURBEntryReadOffset = 0, #endif .ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs, -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 .CrossThreadConstantDataReadLength = cs_prog_data->push.cross_thread.regs, #endif diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 3eeddd01605..ab7857024b1 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -1294,7 +1294,7 @@ void genX(CmdWriteTimestamp)( } } -#if GEN_GEN > 7 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 #define MI_PREDICATE_SRC0 0x2400 #define MI_PREDICATE_SRC1 0x2408 diff --git a/src/mesa/drivers/dri/i965/genX_pipe_control.c b/src/mesa/drivers/dri/i965/genX_pipe_control.c index a6308012b73..55585f548a7 100644 --- a/src/mesa/drivers/dri/i965/genX_pipe_control.c +++ b/src/mesa/drivers/dri/i965/genX_pipe_control.c @@ -407,7 +407,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, * don't skip the ones with only read-cache-invalidate bits set. This * may or may not be a problem... */ - if (GEN_GEN == 7 && GEN_VERSIONx10 != 75) { + if (GEN_VERSIONx10 == 70) { if (flags & PIPE_CONTROL_CS_STALL) { /* If we're doing a CS stall, reset the counter and carry on. */ brw->pipe_controls_since_last_cs_stall = 0; diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 61e9cdf075a..633d57b2864 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -583,7 +583,7 @@ genX(emit_vertices)(struct brw_context *brw) * vertex element may poke over the end of the buffer by 2 bytes. */ const unsigned padding = - (GEN_GEN <= 7 && GEN_VERSIONx10 != 75 && !devinfo->is_baytrail) * 2; + (GEN_VERSIONx10 < 75 && !devinfo->is_baytrail) * 2; const unsigned end = buffer->offset + buffer->size + padding; dw = genX(emit_vertex_buffer_state)(brw, dw, i, buffer->bo, buffer->offset, @@ -864,7 +864,7 @@ genX(emit_index_buffer)(struct brw_context *brw) vf_invalidate_for_ib_48bit_transition(brw); brw_batch_emit(brw, GENX(3DSTATE_INDEX_BUFFER), ib) { -#if GEN_GEN < 8 && GEN_VERSIONx10 != 75 +#if GEN_VERSIONx10 < 75 assert(brw->ib.enable_cut_index == brw->prim_restart.enable_cut_index); ib.CutIndexEnable = brw->ib.enable_cut_index; #endif @@ -897,7 +897,7 @@ static const struct brw_tracked_state genX(index_buffer) = { .emit = genX(emit_index_buffer), }; -#if GEN_VERSIONx10 == 75 || GEN_GEN >= 8 +#if GEN_VERSIONx10 >= 75 static void genX(upload_cut_index)(struct brw_context *brw) { @@ -2579,7 +2579,7 @@ genX(upload_gs_state)(struct brw_context *brw) } #endif -#if GEN_GEN == 7 && GEN_VERSIONx10 != 75 +#if GEN_VERSIONx10 == 70 /** * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages > * Geometry > Geometry Shader > State: @@ -3092,7 +3092,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw) &brw->wm.base, }; - if (GEN_GEN == 7 && GEN_VERSIONx10 != 75 && !devinfo->is_baytrail && + if (GEN_VERSIONx10 == 70 && !devinfo->is_baytrail && stage_states[MESA_SHADER_VERTEX]->push_constants_dirty) gen7_emit_vs_workaround_flush(brw); @@ -3106,7 +3106,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw) brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), pkt) { pkt._3DCommandSubOpcode = push_constant_opcodes[stage]; if (stage_state->prog_data) { -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 /* The Skylake PRM contains the following restriction: * * "The driver must ensure The following case does not occur @@ -4394,7 +4394,7 @@ genX(upload_cs_state)(struct brw_context *brw) .SharedLocalMemorySize = encode_slm_size(GEN_GEN, prog_data->total_shared), .BarrierEnable = cs_prog_data->uses_barrier, -#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75 +#if GEN_VERSIONx10 >= 75 .CrossThreadConstantDataReadLength = cs_prog_data->push.cross_thread.regs, #endif @@ -4925,7 +4925,7 @@ genX(emit_sampler_state_pointers_xs)(UNUSED struct brw_context *brw, }; /* Ivybridge requires a workaround flush before VS packets. */ - if (GEN_GEN == 7 && GEN_VERSIONx10 != 75 && + if (GEN_VERSIONx10 == 70 && stage_state->stage == MESA_SHADER_VERTEX) { gen7_emit_vs_workaround_flush(brw); } @@ -5276,7 +5276,7 @@ genX(update_sampler_state)(struct brw_context *brw, * integer formats. Fall back to CLAMP for now. */ if ((tex_cube_map_seamless || sampler->Attrib.CubeMapSeamless) && - !(GEN_GEN == 7 && GEN_VERSIONx10 != 75 && texObj->_IsIntegerFormat)) { + !(GEN_VERSIONx10 == 70 && texObj->_IsIntegerFormat)) { wrap_s = TCM_CUBE; wrap_t = TCM_CUBE; wrap_r = TCM_CUBE; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
