Module: Mesa
Branch: staging/20.3
Commit: 0c72288c9b182050ca8b65fd1acf447eda05c1f3
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c72288c9b182050ca8b65fd1acf447eda05c1f3

Author: Rhys Perry <[email protected]>
Date:   Mon Feb  1 15:01:57 2021 +0000

radv: correctly enable WGP_MODE for NGG and GS

Previously, we would set WGP_MODE on GFX10+ and then only on GFX10.
Because we used bitwise or, the result was WGP_MODE being set on GFX10+.

We also set the wrong bit, S_00B848_WGP_MODE instead of S_00B228_WGP_MODE.

Signed-off-by: Rhys Perry <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9557>

---

 src/amd/vulkan/radv_shader.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7dab62862ce..955d1b93184 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1008,8 +1008,7 @@ static void radv_postprocess_config(const struct 
radv_device *device,
                                     S_00B02C_EXCP_EN(excp_en);
                break;
        case MESA_SHADER_GEOMETRY:
-               config_out->rsrc1 |= 
S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
-                                    
S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
+               config_out->rsrc1 |= 
S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
                config_out->rsrc2 |= 
S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
                                     S_00B22C_EXCP_EN(excp_en);
                break;
@@ -1062,7 +1061,7 @@ static void radv_postprocess_config(const struct 
radv_device *device,
                }
 
                config_out->rsrc1 |= 
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
-                                    S_00B228_WGP_MODE(1);
+                                    
S_00B228_WGP_MODE(pdevice->rad_info.chip_class == GFX10);
                config_out->rsrc2 |= 
S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
                                     S_00B22C_LDS_SIZE(config_in->lds_size) |
                                     S_00B22C_OC_LDS_EN(es_stage == 
MESA_SHADER_TESS_EVAL);
@@ -1097,7 +1096,8 @@ static void radv_postprocess_config(const struct 
radv_device *device,
                        gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
                }
 
-               config_out->rsrc1 |= 
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
+               config_out->rsrc1 |= 
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
+                                    
S_00B228_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
                config_out->rsrc2 |= 
S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
                                         S_00B22C_OC_LDS_EN(es_type == 
MESA_SHADER_TESS_EVAL);
        } else if (pdevice->rad_info.chip_class >= GFX9 &&

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