Module: Mesa Branch: master Commit: d5b877619d8d37689abd5b4c425ffe90551c7995 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5b877619d8d37689abd5b4c425ffe90551c7995
Author: Marek Olšák <[email protected]> Date: Tue Mar 23 03:43:07 2021 -0400 winsys/amdgpu: remove amdgpu_winsys_bo::ws Reviewed-by: Zoltán Böszörményi <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809> --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 135 +++++++++++++------------- src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 14 +-- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 68 +++++++------ src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 24 +++-- 4 files changed, 126 insertions(+), 115 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 434c43c283d..6ee02ef8d7b 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -51,8 +51,8 @@ static bool amdgpu_bo_wait(struct radeon_winsys *rws, struct pb_buffer *_buf, uint64_t timeout, enum radeon_bo_usage usage) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); - struct amdgpu_winsys *ws = bo->ws; int64_t abs_timeout = 0; if (timeout == 0) { @@ -170,11 +170,10 @@ static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo *bo) bo->max_fences = 0; } -void amdgpu_bo_destroy(void *winsys, struct pb_buffer *_buf) +void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer *_buf) { struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_screen_winsys *sws_iter; - struct amdgpu_winsys *ws = winsys; assert(bo->bo && "must not be called for slab entries"); @@ -232,8 +231,9 @@ void amdgpu_bo_destroy(void *winsys, struct pb_buffer *_buf) FREE(bo); } -static void amdgpu_bo_destroy_or_cache(void *winsys, struct pb_buffer *_buf) +static void amdgpu_bo_destroy_or_cache(struct radeon_winsys *rws, struct pb_buffer *_buf) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); assert(bo->bo); /* slab buffers have a separate vtbl */ @@ -241,7 +241,7 @@ static void amdgpu_bo_destroy_or_cache(void *winsys, struct pb_buffer *_buf) if (bo->u.real.use_reusable_pool) pb_cache_add_buffer(bo->cache_entry); else - amdgpu_bo_destroy(winsys, _buf); + amdgpu_bo_destroy(ws, _buf); } static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys *ws) @@ -255,13 +255,15 @@ static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys *ws) pb_cache_release_all_buffers(&ws->bo_cache); } -static bool amdgpu_bo_do_map(struct amdgpu_winsys_bo *bo, void **cpu) +static bool amdgpu_bo_do_map(struct radeon_winsys *rws, struct amdgpu_winsys_bo *bo, void **cpu) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); + assert(!(bo->base.usage & RADEON_FLAG_SPARSE) && bo->bo && !bo->u.real.is_user_ptr); int r = amdgpu_bo_cpu_map(bo->bo, cpu); if (r) { /* Clean up buffer managers and try again. */ - amdgpu_clean_up_buffer_managers(bo->ws); + amdgpu_clean_up_buffer_managers(ws); r = amdgpu_bo_cpu_map(bo->bo, cpu); if (r) return false; @@ -269,10 +271,10 @@ static bool amdgpu_bo_do_map(struct amdgpu_winsys_bo *bo, void **cpu) if (p_atomic_inc_return(&bo->u.real.map_count) == 1) { if (bo->base.placement & RADEON_DOMAIN_VRAM) - bo->ws->mapped_vram += bo->base.size; + ws->mapped_vram += bo->base.size; else if (bo->base.placement & RADEON_DOMAIN_GTT) - bo->ws->mapped_gtt += bo->base.size; - bo->ws->num_mapped_buffers++; + ws->mapped_gtt += bo->base.size; + ws->num_mapped_buffers++; } return true; @@ -283,6 +285,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, struct radeon_cmdbuf *rcs, enum pipe_map_flags usage) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; struct amdgpu_winsys_bo *real; struct amdgpu_cs *cs = rcs ? amdgpu_cs(rcs) : NULL; @@ -366,7 +369,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, RADEON_USAGE_READWRITE); } - bo->ws->buffer_wait_time += os_time_get_nano() - time; + ws->buffer_wait_time += os_time_get_nano() - time; } } @@ -385,7 +388,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, if (real->u.real.is_user_ptr) { cpu = real->u.real.cpu_ptr; } else { - if (!amdgpu_bo_do_map(real, &cpu)) + if (!amdgpu_bo_do_map(rws, real, &cpu)) return NULL; } } else { @@ -396,7 +399,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, * be atomic thanks to the lock. */ cpu = real->u.real.cpu_ptr; if (!cpu) { - if (!amdgpu_bo_do_map(real, &cpu)) { + if (!amdgpu_bo_do_map(rws, real, &cpu)) { simple_mtx_unlock(&real->lock); return NULL; } @@ -411,6 +414,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, void amdgpu_bo_unmap(struct radeon_winsys *rws, struct pb_buffer *buf) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; struct amdgpu_winsys_bo *real; @@ -427,25 +431,24 @@ void amdgpu_bo_unmap(struct radeon_winsys *rws, struct pb_buffer *buf) "too many unmaps or forgot RADEON_MAP_TEMPORARY flag"); if (real->base.placement & RADEON_DOMAIN_VRAM) - real->ws->mapped_vram -= real->base.size; + ws->mapped_vram -= real->base.size; else if (real->base.placement & RADEON_DOMAIN_GTT) - real->ws->mapped_gtt -= real->base.size; - real->ws->num_mapped_buffers--; + ws->mapped_gtt -= real->base.size; + ws->num_mapped_buffers--; } amdgpu_bo_cpu_unmap(real->bo); } static const struct pb_vtbl amdgpu_winsys_bo_vtbl = { - amdgpu_bo_destroy_or_cache + /* Cast to void* because one of the function parameters is a struct pointer instead of void*. */ + (void*)amdgpu_bo_destroy_or_cache /* other functions are never called */ }; -static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo *bo) +static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo *bo) { #if DEBUG - struct amdgpu_winsys *ws = bo->ws; - assert(bo->bo); if (ws->debug_all_bos) { @@ -592,7 +595,6 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, bo->base.alignment = alignment; bo->base.size = size; bo->base.vtbl = &amdgpu_winsys_bo_vtbl; - bo->ws = ws; bo->bo = buf_handle; bo->va = va; bo->u.real.va_handle = va_handle; @@ -607,7 +609,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->u.real.kms_handle); - amdgpu_add_buffer_to_global_list(bo); + amdgpu_add_buffer_to_global_list(ws, bo); return bo; @@ -622,10 +624,8 @@ error_bo_alloc: return NULL; } -bool amdgpu_bo_can_reclaim(void *winsys, struct pb_buffer *_buf) +bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *ws, struct pb_buffer *_buf) { - struct amdgpu_winsys *ws = winsys; - return amdgpu_bo_wait(&ws->dummy_ws.base, _buf, 0, RADEON_USAGE_READWRITE); } @@ -633,7 +633,7 @@ bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry) { struct amdgpu_winsys_bo *bo = container_of(entry, struct amdgpu_winsys_bo, u.slab.entry); - return amdgpu_bo_can_reclaim(NULL, &bo->base); + return amdgpu_bo_can_reclaim(priv, &bo->base); } static struct pb_slabs *get_slabs(struct amdgpu_winsys *ws, uint64_t size, @@ -653,38 +653,40 @@ static struct pb_slabs *get_slabs(struct amdgpu_winsys *ws, uint64_t size, return NULL; } -static unsigned get_slab_wasted_size(struct amdgpu_winsys_bo *bo) +static unsigned get_slab_wasted_size(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo *bo) { assert(bo->base.size <= bo->u.slab.entry.entry_size); assert(bo->base.size < bo->base.alignment || - bo->base.size < 1 << bo->ws->bo_slabs[0].min_order || + bo->base.size < 1 << ws->bo_slabs[0].min_order || bo->base.size > bo->u.slab.entry.entry_size / 2); return bo->u.slab.entry.entry_size - bo->base.size; } -static void amdgpu_bo_slab_destroy(void *winsys, struct pb_buffer *_buf) +static void amdgpu_bo_slab_destroy(struct radeon_winsys *rws, struct pb_buffer *_buf) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); assert(!bo->bo); if (bo->base.usage & RADEON_FLAG_ENCRYPTED) - pb_slab_free(get_slabs(bo->ws, + pb_slab_free(get_slabs(ws, bo->base.size, RADEON_FLAG_ENCRYPTED), &bo->u.slab.entry); else - pb_slab_free(get_slabs(bo->ws, + pb_slab_free(get_slabs(ws, bo->base.size, 0), &bo->u.slab.entry); if (bo->base.placement & RADEON_DOMAIN_VRAM) - bo->ws->slab_wasted_vram -= get_slab_wasted_size(bo); + ws->slab_wasted_vram -= get_slab_wasted_size(ws, bo); else - bo->ws->slab_wasted_gtt -= get_slab_wasted_size(bo); + ws->slab_wasted_gtt -= get_slab_wasted_size(ws, bo); } static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl = { - amdgpu_bo_slab_destroy + /* Cast to void* because one of the function parameters is a struct pointer instead of void*. */ + (void*)amdgpu_bo_slab_destroy /* other functions are never called */ }; @@ -789,7 +791,6 @@ static struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, bo->base.alignment = get_slab_entry_alignment(ws, entry_size); bo->base.size = entry_size; bo->base.vtbl = &amdgpu_winsys_bo_slab_vtbl; - bo->ws = ws; bo->va = slab->buffer->va + i * entry_size; bo->base.placement = domains; bo->unique_id = base_id + i; @@ -819,7 +820,7 @@ static struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, return &slab->base; fail_buffer: - amdgpu_winsys_bo_reference(&slab->buffer, NULL); + amdgpu_winsys_bo_reference(ws, &slab->buffer, NULL); fail: FREE(slab); return NULL; @@ -839,10 +840,9 @@ struct pb_slab *amdgpu_bo_slab_alloc_normal(void *priv, unsigned heap, return amdgpu_bo_slab_alloc(priv, heap, entry_size, group_index, false); } -void amdgpu_bo_slab_free(void *priv, struct pb_slab *pslab) +void amdgpu_bo_slab_free(struct amdgpu_winsys *ws, struct pb_slab *pslab) { struct amdgpu_slab *slab = amdgpu_slab(pslab); - struct amdgpu_winsys *ws = slab->buffer->ws; unsigned slab_size = slab->buffer->base.size; assert(slab->base.num_entries * slab->entry_size <= slab_size); @@ -857,7 +857,7 @@ void amdgpu_bo_slab_free(void *priv, struct pb_slab *pslab) } FREE(slab->entries); - amdgpu_winsys_bo_reference(&slab->buffer, NULL); + amdgpu_winsys_bo_reference(ws, &slab->buffer, NULL); FREE(slab); } @@ -922,7 +922,8 @@ sparse_dump(struct amdgpu_winsys_bo *bo, const char *func) * which will be reflected by a change to *pnum_pages. */ static struct amdgpu_sparse_backing * -sparse_backing_alloc(struct amdgpu_winsys_bo *bo, uint32_t *pstart_page, uint32_t *pnum_pages) +sparse_backing_alloc(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo *bo, + uint32_t *pstart_page, uint32_t *pnum_pages) { struct amdgpu_sparse_backing *best_backing; unsigned best_idx; @@ -970,7 +971,7 @@ sparse_backing_alloc(struct amdgpu_winsys_bo *bo, uint32_t *pstart_page, uint32_ bo->base.size - (uint64_t)bo->u.sparse.num_backing_pages * RADEON_SPARSE_PAGE_SIZE); size = MAX2(size, RADEON_SPARSE_PAGE_SIZE); - buf = amdgpu_bo_create(bo->ws, size, RADEON_SPARSE_PAGE_SIZE, + buf = amdgpu_bo_create(ws, size, RADEON_SPARSE_PAGE_SIZE, bo->base.placement, (bo->base.usage & ~RADEON_FLAG_SPARSE & /* Set the interprocess sharing flag to disable pb_cache because @@ -1012,11 +1013,9 @@ sparse_backing_alloc(struct amdgpu_winsys_bo *bo, uint32_t *pstart_page, uint32_ } static void -sparse_free_backing_buffer(struct amdgpu_winsys_bo *bo, +sparse_free_backing_buffer(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo *bo, struct amdgpu_sparse_backing *backing) { - struct amdgpu_winsys *ws = backing->bo->ws; - bo->u.sparse.num_backing_pages -= backing->bo->base.size / RADEON_SPARSE_PAGE_SIZE; simple_mtx_lock(&ws->bo_fence_lock); @@ -1024,7 +1023,7 @@ sparse_free_backing_buffer(struct amdgpu_winsys_bo *bo, simple_mtx_unlock(&ws->bo_fence_lock); list_del(&backing->list); - amdgpu_winsys_bo_reference(&backing->bo, NULL); + amdgpu_winsys_bo_reference(ws, &backing->bo, NULL); FREE(backing->chunks); FREE(backing); } @@ -1034,7 +1033,7 @@ sparse_free_backing_buffer(struct amdgpu_winsys_bo *bo, * free structure. */ static bool -sparse_backing_free(struct amdgpu_winsys_bo *bo, +sparse_backing_free(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo *bo, struct amdgpu_sparse_backing *backing, uint32_t start_page, uint32_t num_pages) { @@ -1089,19 +1088,20 @@ sparse_backing_free(struct amdgpu_winsys_bo *bo, if (backing->num_chunks == 1 && backing->chunks[0].begin == 0 && backing->chunks[0].end == backing->bo->base.size / RADEON_SPARSE_PAGE_SIZE) - sparse_free_backing_buffer(bo, backing); + sparse_free_backing_buffer(ws, bo, backing); return true; } -static void amdgpu_bo_sparse_destroy(void *winsys, struct pb_buffer *_buf) +static void amdgpu_bo_sparse_destroy(struct radeon_winsys *rws, struct pb_buffer *_buf) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); int r; assert(!bo->bo && bo->base.usage & RADEON_FLAG_SPARSE); - r = amdgpu_bo_va_op_raw(bo->ws->dev, NULL, 0, + r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, (uint64_t)bo->u.sparse.num_va_pages * RADEON_SPARSE_PAGE_SIZE, bo->va, 0, AMDGPU_VA_OP_CLEAR); if (r) { @@ -1109,7 +1109,7 @@ static void amdgpu_bo_sparse_destroy(void *winsys, struct pb_buffer *_buf) } while (!list_is_empty(&bo->u.sparse.backing)) { - sparse_free_backing_buffer(bo, + sparse_free_backing_buffer(ws, bo, container_of(bo->u.sparse.backing.next, struct amdgpu_sparse_backing, list)); } @@ -1121,7 +1121,8 @@ static void amdgpu_bo_sparse_destroy(void *winsys, struct pb_buffer *_buf) } static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl = { - amdgpu_bo_sparse_destroy + /* Cast to void* because one of the function parameters is a struct pointer instead of void*. */ + (void*)amdgpu_bo_sparse_destroy /* other functions are never called */ }; @@ -1151,7 +1152,6 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size, bo->base.alignment = RADEON_SPARSE_PAGE_SIZE; bo->base.size = size; bo->base.vtbl = &amdgpu_winsys_bo_sparse_vtbl; - bo->ws = ws; bo->base.placement = domain; bo->unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1); bo->base.usage = flags; @@ -1174,7 +1174,7 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size, if (r) goto error_va_alloc; - r = amdgpu_bo_va_op_raw(bo->ws->dev, NULL, 0, size, bo->va, + r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, size, bo->va, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP); if (r) goto error_va_map; @@ -1195,6 +1195,7 @@ static bool amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer *buf, uint64_t offset, uint64_t size, bool commit) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buf); struct amdgpu_sparse_commitment *comm; uint32_t va_page, end_va_page; @@ -1238,13 +1239,13 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer *buf, uint32_t backing_start, backing_size; backing_size = va_page - span_va_page; - backing = sparse_backing_alloc(bo, &backing_start, &backing_size); + backing = sparse_backing_alloc(ws, bo, &backing_start, &backing_size); if (!backing) { ok = false; goto out; } - r = amdgpu_bo_va_op_raw(bo->ws->dev, backing->bo->bo, + r = amdgpu_bo_va_op_raw(ws->dev, backing->bo->bo, (uint64_t)backing_start * RADEON_SPARSE_PAGE_SIZE, (uint64_t)backing_size * RADEON_SPARSE_PAGE_SIZE, bo->va + (uint64_t)span_va_page * RADEON_SPARSE_PAGE_SIZE, @@ -1253,7 +1254,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer *buf, AMDGPU_VM_PAGE_EXECUTABLE, AMDGPU_VA_OP_REPLACE); if (r) { - ok = sparse_backing_free(bo, backing, backing_start, backing_size); + ok = sparse_backing_free(ws, bo, backing, backing_start, backing_size); assert(ok && "sufficient memory should already be allocated"); ok = false; @@ -1270,7 +1271,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer *buf, } } } else { - r = amdgpu_bo_va_op_raw(bo->ws->dev, NULL, 0, + r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, (uint64_t)(end_va_page - va_page) * RADEON_SPARSE_PAGE_SIZE, bo->va + (uint64_t)va_page * RADEON_SPARSE_PAGE_SIZE, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_REPLACE); @@ -1306,7 +1307,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer *buf, span_pages++; } - if (!sparse_backing_free(bo, backing, backing_start, span_pages)) { + if (!sparse_backing_free(ws, bo, backing, backing_start, span_pages)) { /* Couldn't allocate tracking data structures, so we have to leak */ fprintf(stderr, "amdgpu: leaking PRT backing memory\n"); ok = false; @@ -1325,6 +1326,7 @@ static void amdgpu_buffer_get_metadata(struct radeon_winsys *rws, struct radeon_bo_metadata *md, struct radeon_surf *surf) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_bo_info info = {0}; int r; @@ -1335,7 +1337,7 @@ static void amdgpu_buffer_get_metadata(struct radeon_winsys *rws, if (r) return; - ac_surface_set_bo_metadata(&bo->ws->info, surf, info.metadata.tiling_info, + ac_surface_set_bo_metadata(&ws->info, surf, info.metadata.tiling_info, &md->mode); md->size_metadata = info.metadata.size_metadata; @@ -1347,12 +1349,13 @@ static void amdgpu_buffer_set_metadata(struct radeon_winsys *rws, struct radeon_bo_metadata *md, struct radeon_surf *surf) { + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_bo_metadata metadata = {0}; assert(bo->bo && "must not be called for slab entries"); - ac_surface_get_bo_metadata(&bo->ws->info, surf, &metadata.tiling_info); + ac_surface_get_bo_metadata(&ws->info, surf, &metadata.tiling_info); metadata.size_metadata = md->size_metadata; memcpy(metadata.umd_metadata, md->metadata, sizeof(md->metadata)); @@ -1435,9 +1438,9 @@ amdgpu_bo_create(struct amdgpu_winsys *ws, assert(alignment <= bo->base.alignment); if (domain & RADEON_DOMAIN_VRAM) - ws->slab_wasted_vram += get_slab_wasted_size(bo); + ws->slab_wasted_vram += get_slab_wasted_size(ws, bo); else - ws->slab_wasted_gtt += get_slab_wasted_size(bo); + ws->slab_wasted_gtt += get_slab_wasted_size(ws, bo); return &bo->base; } @@ -1592,7 +1595,6 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws, bo->bo = result.buf_handle; bo->base.size = result.alloc_size; bo->base.vtbl = &amdgpu_winsys_bo_vtbl; - bo->ws = ws; bo->va = va; bo->u.real.va_handle = va_handle; bo->base.placement = initial; @@ -1607,7 +1609,7 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws, amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->u.real.kms_handle); - amdgpu_add_buffer_to_global_list(bo); + amdgpu_add_buffer_to_global_list(ws, bo); _mesa_hash_table_insert(ws->bo_export_table, bo->bo, bo); simple_mtx_unlock(&ws->bo_export_table_lock); @@ -1629,8 +1631,8 @@ static bool amdgpu_bo_get_handle(struct radeon_winsys *rws, struct winsys_handle *whandle) { struct amdgpu_screen_winsys *sws = amdgpu_screen_winsys(rws); + struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer); - struct amdgpu_winsys *ws = bo->ws; enum amdgpu_bo_handle_type type; struct hash_entry *entry; int r; @@ -1742,7 +1744,6 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct radeon_winsys *rws, bo->base.alignment = 0; bo->base.size = size; bo->base.vtbl = &amdgpu_winsys_bo_vtbl; - bo->ws = ws; bo->u.real.cpu_ptr = pointer; bo->va = va; bo->u.real.va_handle = va_handle; @@ -1751,7 +1752,7 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct radeon_winsys *rws, ws->allocated_gtt += aligned_size; - amdgpu_add_buffer_to_global_list(bo); + amdgpu_add_buffer_to_global_list(ws, bo); amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->u.real.kms_handle); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h index 95007555fe9..895d4fb7b5e 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h @@ -92,8 +92,6 @@ struct amdgpu_winsys_bo { } sparse; } u; - struct amdgpu_winsys *ws; - amdgpu_bo_handle bo; /* NULL for slab entries and sparse buffers */ uint32_t unique_id; @@ -119,13 +117,13 @@ struct amdgpu_slab { struct amdgpu_winsys_bo *entries; }; -bool amdgpu_bo_can_reclaim(void *winsys, struct pb_buffer *_buf); +bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *ws, struct pb_buffer *_buf); struct pb_buffer *amdgpu_bo_create(struct amdgpu_winsys *ws, uint64_t size, unsigned alignment, enum radeon_bo_domain domain, enum radeon_bo_flag flags); -void amdgpu_bo_destroy(void *winsys, struct pb_buffer *_buf); +void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer *_buf); void *amdgpu_bo_map(struct radeon_winsys *rws, struct pb_buffer *buf, struct radeon_cmdbuf *rcs, @@ -140,7 +138,7 @@ struct pb_slab *amdgpu_bo_slab_alloc_encrypted(void *priv, unsigned heap, struct pb_slab *amdgpu_bo_slab_alloc_normal(void *priv, unsigned heap, unsigned entry_size, unsigned group_index); -void amdgpu_bo_slab_free(void *priv, struct pb_slab *slab); +void amdgpu_bo_slab_free(struct amdgpu_winsys *ws, struct pb_slab *slab); static inline struct amdgpu_winsys_bo *amdgpu_winsys_bo(struct pb_buffer *bo) @@ -155,10 +153,12 @@ struct amdgpu_slab *amdgpu_slab(struct pb_slab *slab) } static inline -void amdgpu_winsys_bo_reference(struct amdgpu_winsys_bo **dst, +void amdgpu_winsys_bo_reference(struct amdgpu_winsys *ws, + struct amdgpu_winsys_bo **dst, struct amdgpu_winsys_bo *src) { - pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src); + radeon_bo_reference(&ws->dummy_ws.base, + (struct pb_buffer**)dst, (struct pb_buffer*)src); } #endif diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 8e957288e08..36c15fd3542 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -457,7 +457,8 @@ int amdgpu_lookup_buffer_any_type(struct amdgpu_cs_context *cs, struct amdgpu_wi } static int -amdgpu_do_add_real_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo) +amdgpu_do_add_real_buffer(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs, + struct amdgpu_winsys_bo *bo) { struct amdgpu_cs_buffer *buffer; int idx; @@ -488,7 +489,7 @@ amdgpu_do_add_real_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo buffer = &cs->real_buffers[idx]; memset(buffer, 0, sizeof(*buffer)); - amdgpu_winsys_bo_reference(&buffer->bo, bo); + amdgpu_winsys_bo_reference(ws, &buffer->bo, bo); cs->num_real_buffers++; return idx; @@ -505,7 +506,7 @@ amdgpu_lookup_or_add_real_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs *ac if (idx >= 0) return idx; - idx = amdgpu_do_add_real_buffer(cs, bo); + idx = amdgpu_do_add_real_buffer(acs->ctx->ws, cs, bo); hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1); cs->buffer_indices_hashlist[hash] = idx; @@ -518,7 +519,8 @@ amdgpu_lookup_or_add_real_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs *ac return idx; } -static int amdgpu_lookup_or_add_slab_buffer(struct radeon_cmdbuf *rcs, +static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_winsys *ws, + struct radeon_cmdbuf *rcs, struct amdgpu_cs *acs, struct amdgpu_winsys_bo *bo) { @@ -557,7 +559,7 @@ static int amdgpu_lookup_or_add_slab_buffer(struct radeon_cmdbuf *rcs, buffer = &cs->slab_buffers[idx]; memset(buffer, 0, sizeof(*buffer)); - amdgpu_winsys_bo_reference(&buffer->bo, bo); + amdgpu_winsys_bo_reference(ws, &buffer->bo, bo); buffer->u.slab.real_idx = real_idx; cs->num_slab_buffers++; @@ -567,7 +569,8 @@ static int amdgpu_lookup_or_add_slab_buffer(struct radeon_cmdbuf *rcs, return idx; } -static int amdgpu_lookup_or_add_sparse_buffer(struct radeon_cmdbuf *rcs, +static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_winsys *ws, + struct radeon_cmdbuf *rcs, struct amdgpu_cs *acs, struct amdgpu_winsys_bo *bo) { @@ -601,7 +604,7 @@ static int amdgpu_lookup_or_add_sparse_buffer(struct radeon_cmdbuf *rcs, buffer = &cs->sparse_buffers[idx]; memset(buffer, 0, sizeof(*buffer)); - amdgpu_winsys_bo_reference(&buffer->bo, bo); + amdgpu_winsys_bo_reference(ws, &buffer->bo, bo); cs->num_sparse_buffers++; hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1); @@ -650,7 +653,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs, if (!(bo->base.usage & RADEON_FLAG_SPARSE)) { if (!bo->bo) { - index = amdgpu_lookup_or_add_slab_buffer(rcs, acs, bo); + index = amdgpu_lookup_or_add_slab_buffer(acs->ctx->ws, rcs, acs, bo); if (index < 0) return 0; @@ -667,7 +670,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs, buffer = &cs->real_buffers[index]; } else { - index = amdgpu_lookup_or_add_sparse_buffer(rcs, acs, bo); + index = amdgpu_lookup_or_add_sparse_buffer(acs->ctx->ws, rcs, acs, bo); if (index < 0) return 0; @@ -731,12 +734,12 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, mapped = amdgpu_bo_map(&ws->dummy_ws.base, pb, NULL, PIPE_MAP_WRITE); if (!mapped) { - pb_reference(&pb, NULL); + radeon_bo_reference(&ws->dummy_ws.base, &pb, NULL); return false; } - pb_reference(&ib->big_ib_buffer, pb); - pb_reference(&pb, NULL); + radeon_bo_reference(&ws->dummy_ws.base, &ib->big_ib_buffer, pb); + radeon_bo_reference(&ws->dummy_ws.base, &pb, NULL); ib->ib_mapped = mapped; ib->used_ib_space = 0; @@ -906,18 +909,18 @@ static void cleanup_fence_list(struct amdgpu_fence_list *fences) fences->num = 0; } -static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs) +static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs) { unsigned i; for (i = 0; i < cs->num_real_buffers; i++) { - amdgpu_winsys_bo_reference(&cs->real_buffers[i].bo, NULL); + amdgpu_winsys_bo_reference(ws, &cs->real_buffers[i].bo, NULL); } for (i = 0; i < cs->num_slab_buffers; i++) { - amdgpu_winsys_bo_reference(&cs->slab_buffers[i].bo, NULL); + amdgpu_winsys_bo_reference(ws, &cs->slab_buffers[i].bo, NULL); } for (i = 0; i < cs->num_sparse_buffers; i++) { - amdgpu_winsys_bo_reference(&cs->sparse_buffers[i].bo, NULL); + amdgpu_winsys_bo_reference(ws, &cs->sparse_buffers[i].bo, NULL); } cleanup_fence_list(&cs->fence_dependencies); cleanup_fence_list(&cs->syncobj_dependencies); @@ -934,9 +937,9 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs) cs->last_added_bo = NULL; } -static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *cs) +static void amdgpu_destroy_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs) { - amdgpu_cs_context_cleanup(cs); + amdgpu_cs_context_cleanup(ws, cs); FREE(cs->real_buffers); FREE(cs->slab_buffers); FREE(cs->sparse_buffers); @@ -988,7 +991,7 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, } if (!amdgpu_init_cs_context(ctx->ws, &cs->csc2, ring_type)) { - amdgpu_destroy_cs_context(&cs->csc1); + amdgpu_destroy_cs_context(ctx->ws, &cs->csc1); FREE(cs); return false; } @@ -1001,8 +1004,8 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, rcs->priv = cs; if (!amdgpu_get_new_ib(ctx->ws, rcs, &cs->main, cs)) { - amdgpu_destroy_cs_context(&cs->csc2); - amdgpu_destroy_cs_context(&cs->csc1); + amdgpu_destroy_cs_context(ctx->ws, &cs->csc2); + amdgpu_destroy_cs_context(ctx->ws, &cs->csc1); FREE(cs); rcs->priv = NULL; return false; @@ -1066,7 +1069,7 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i map = (uint32_t*)amdgpu_bo_map(&ws->dummy_ws.base, preamble_bo, NULL, PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY); if (!map) { - pb_reference(&preamble_bo, NULL); + radeon_bo_reference(&ws->dummy_ws.base, &preamble_bo, NULL); return false; } @@ -1399,7 +1402,8 @@ static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf *rws, * This is done late, during submission, to keep the buffer list short before * submit, and to avoid managing fences for the backing buffers. */ -static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context *cs) +static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_winsys *ws, + struct amdgpu_cs_context *cs) { for (unsigned i = 0; i < cs->num_sparse_buffers; ++i) { struct amdgpu_cs_buffer *buffer = &cs->sparse_buffers[i]; @@ -1411,7 +1415,7 @@ static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context *cs) /* We can directly add the buffer here, because we know that each * backing buffer occurs only once. */ - int idx = amdgpu_do_add_real_buffer(cs, backing->bo); + int idx = amdgpu_do_add_real_buffer(ws, cs, backing->bo); if (idx < 0) { fprintf(stderr, "%s: failed to add buffer\n", __FUNCTION__); simple_mtx_unlock(&bo->lock); @@ -1467,7 +1471,7 @@ static void amdgpu_cs_submit_ib(void *job, int thread_index) } else #endif { - if (!amdgpu_add_sparse_backing_buffers(cs)) { + if (!amdgpu_add_sparse_backing_buffers(ws, cs)) { fprintf(stderr, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n"); r = -ENOMEM; goto cleanup; @@ -1727,7 +1731,7 @@ cleanup: for (i = 0; i < cs->num_sparse_buffers; i++) p_atomic_dec(&cs->sparse_buffers[i].bo->num_active_ioctls); - amdgpu_cs_context_cleanup(cs); + amdgpu_cs_context_cleanup(ws, cs); } /* Make sure the previous submission is completed. */ @@ -1865,7 +1869,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, } else { if (flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION) cs->csc->secure = !cs->csc->secure; - amdgpu_cs_context_cleanup(cs->csc); + amdgpu_cs_context_cleanup(ws, cs->csc); } amdgpu_get_new_ib(ws, rcs, &cs->main, cs); @@ -1898,14 +1902,14 @@ static void amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) amdgpu_cs_sync_flush(rcs); util_queue_fence_destroy(&cs->flush_completed); p_atomic_dec(&cs->ctx->ws->num_cs); - pb_reference(&cs->preamble_ib_bo, NULL); - pb_reference(&cs->main.big_ib_buffer, NULL); + radeon_bo_reference(&cs->ctx->ws->dummy_ws.base, &cs->preamble_ib_bo, NULL); + radeon_bo_reference(&cs->ctx->ws->dummy_ws.base, &cs->main.big_ib_buffer, NULL); FREE(rcs->prev); - pb_reference(&cs->compute_ib.big_ib_buffer, NULL); + radeon_bo_reference(&cs->ctx->ws->dummy_ws.base, &cs->compute_ib.big_ib_buffer, NULL); if (cs->compute_ib.rcs) FREE(cs->compute_ib.rcs->prev); - amdgpu_destroy_cs_context(&cs->csc1); - amdgpu_destroy_cs_context(&cs->csc2); + amdgpu_destroy_cs_context(cs->ctx->ws, &cs->csc1); + amdgpu_destroy_cs_context(cs->ctx->ws, &cs->csc2); amdgpu_fence_reference(&cs->next_fence, NULL); FREE(cs); } diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index e8ee6decfca..5ee8ed41619 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -443,8 +443,10 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config, /* Create managers. */ pb_cache_init(&aws->bo_cache, RADEON_MAX_CACHED_HEAPS, 500000, aws->check_vm ? 1.0f : 2.0f, 0, - (aws->info.vram_size + aws->info.gart_size) / 8, ws, - amdgpu_bo_destroy, amdgpu_bo_can_reclaim); + (aws->info.vram_size + aws->info.gart_size) / 8, aws, + /* Cast to void* because one of the function parameters + * is a struct pointer instead of void*. */ + (void*)amdgpu_bo_destroy, (void*)amdgpu_bo_can_reclaim); unsigned min_slab_order = 8; /* 256 bytes */ unsigned max_slab_order = 20; /* 1 MB (slab size = 2 MB) */ @@ -463,7 +465,9 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config, aws, amdgpu_bo_can_reclaim_slab, amdgpu_bo_slab_alloc_normal, - amdgpu_bo_slab_free)) { + /* Cast to void* because one of the function parameters + * is a struct pointer instead of void*. */ + (void*)amdgpu_bo_slab_free)) { amdgpu_winsys_destroy(&ws->base); simple_mtx_unlock(&dev_tab_mutex); return NULL; @@ -476,7 +480,9 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config, aws, amdgpu_bo_can_reclaim_slab, amdgpu_bo_slab_alloc_encrypted, - amdgpu_bo_slab_free)) { + /* Cast to void* because one of the function parameters + * is a struct pointer instead of void*. */ + (void*)amdgpu_bo_slab_free)) { amdgpu_winsys_destroy(&ws->base); simple_mtx_unlock(&dev_tab_mutex); return NULL; @@ -536,6 +542,11 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config, amdgpu_cs_init_functions(ws); amdgpu_surface_init_functions(ws); + simple_mtx_lock(&aws->sws_list_lock); + ws->next = aws->sws_list; + aws->sws_list = ws; + simple_mtx_unlock(&aws->sws_list_lock); + /* Create the screen at the end. The winsys must be initialized * completely. * @@ -548,11 +559,6 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config, return NULL; } - simple_mtx_lock(&aws->sws_list_lock); - ws->next = aws->sws_list; - aws->sws_list = ws; - simple_mtx_unlock(&aws->sws_list_lock); - unlock: /* We must unlock the mutex once the winsys is fully initialized, so that * other threads attempting to create the winsys from the same fd will _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
