Module: Mesa Branch: master Commit: b61efd53b464615c084763d9dfff8eda07afbe3a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b61efd53b464615c084763d9dfff8eda07afbe3a
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Date: Mon Mar 8 15:45:50 2021 +0100 radv: Support DCC without a fast clear value. For imported images we can't have one in the associated memory. Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998> --- src/amd/vulkan/radv_cmd_buffer.c | 35 ++++++++++++++++++++++++----------- src/amd/vulkan/radv_meta_clear.c | 4 ++++ src/amd/vulkan/radv_private.h | 10 ++++++++++ 3 files changed, 38 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f590be50411..3e01bfc63ef 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2207,23 +2207,29 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, uint32_t color_values[2]) { struct radeon_cmdbuf *cs = cmd_buffer->cs; - uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel); uint32_t level_count = radv_get_levelCount(image, range); uint32_t count = 2 * level_count; assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel)); - radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating)); - radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | - S_370_WR_CONFIRM(1) | - S_370_ENGINE_SEL(V_370_PFP)); - radeon_emit(cs, va); - radeon_emit(cs, va >> 32); + if (radv_image_has_clear_value(image)) { + uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel); - for (uint32_t l = 0; l < level_count; l++) { - radeon_emit(cs, color_values[0]); - radeon_emit(cs, color_values[1]); + radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating)); + radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | + S_370_WR_CONFIRM(1) | + S_370_ENGINE_SEL(V_370_PFP)); + radeon_emit(cs, va); + radeon_emit(cs, va >> 32); + + for (uint32_t l = 0; l < level_count; l++) { + radeon_emit(cs, color_values[0]); + radeon_emit(cs, color_values[1]); + } + } else { + /* Some default value we can set in the update. */ + assert(color_values[0] == 0 && color_values[1] == 0); } } @@ -2264,12 +2270,19 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, { struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_image *image = iview->image; - uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip); if (!radv_image_has_cmask(image) && !radv_dcc_enabled(image, iview->base_mip)) return; + if (!radv_image_has_clear_value(image)) { + uint32_t color_values[2] = {0, 0}; + radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx, + color_values); + return; + } + + uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip); uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c; if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) { diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 24c3b8f74f1..f49bf3b23e4 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1636,6 +1636,10 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, clear_color, &clear_value)) return false; + if (!radv_image_has_clear_value(iview->image) && + (clear_color[0] != 0 || clear_color[1] != 0)) + return false; + if (radv_dcc_enabled(iview->image, iview->base_mip)) { bool can_avoid_fast_clear_elim; uint32_t reset_value; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index c959758cff6..de86a68b7d0 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2022,10 +2022,18 @@ radv_image_tile_stencil_disabled(const struct radv_device *device, } } +static inline bool +radv_image_has_clear_value(const struct radv_image *image) +{ + return image->clear_value_offset != 0; +} + static inline uint64_t radv_image_get_fast_clear_va(const struct radv_image *image, uint32_t base_level) { + assert(radv_image_has_clear_value(image)); + uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset + base_level * 8; return va; @@ -2062,6 +2070,8 @@ static inline uint64_t radv_get_ds_clear_value_va(const struct radv_image *image, uint32_t base_level) { + assert(radv_image_has_clear_value(image)); + uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset + base_level * 8; return va; _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
