Module: Mesa Branch: master Commit: 34fd07aa56a158c5eee38e0bd531448a600fe37f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34fd07aa56a158c5eee38e0bd531448a600fe37f
Author: Marek Olšák <marek.ol...@amd.com> Date: Mon Apr 12 00:54:37 2021 -0400 ac/surface: unify htile_levels and dcc_levels as meta_levels Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-pra...@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083> --- src/amd/common/ac_surface.c | 8 ++++---- src/amd/common/ac_surface.h | 9 +++------ src/amd/vulkan/radv_meta_clear.c | 8 ++++---- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index ffb81cf0a84..c03206d00e3 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1806,8 +1806,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->num_htile_levels = in->numMipLevels; for (unsigned i = 0; i < in->numMipLevels; i++) { - surf->u.gfx9.htile_levels[i].offset = meta_mip_info[i].offset; - surf->u.gfx9.htile_levels[i].size = meta_mip_info[i].sliceSize; + surf->u.gfx9.meta_levels[i].offset = meta_mip_info[i].offset; + surf->u.gfx9.meta_levels[i].size = meta_mip_info[i].sliceSize; if (meta_mip_info[i].inMiptail) { /* GFX10 can only compress the first level @@ -1919,8 +1919,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ * - Flush TC L2 after rendering. */ for (unsigned i = 0; i < in->numMipLevels; i++) { - surf->u.gfx9.dcc_levels[i].offset = meta_mip_info[i].offset; - surf->u.gfx9.dcc_levels[i].size = meta_mip_info[i].sliceSize; + surf->u.gfx9.meta_levels[i].offset = meta_mip_info[i].offset; + surf->u.gfx9.meta_levels[i].size = meta_mip_info[i].sliceSize; if (meta_mip_info[i].inMiptail) { /* GFX10 can only compress the first level diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index ec8e3130818..b4964aa6c35 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -188,6 +188,9 @@ struct gfx9_surf_layout { /* Offset within slice in bytes, only valid for prt images. */ uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS]; + /* DCC or HTILE level info */ + struct gfx9_surf_level meta_levels[RADEON_SURF_MAX_LEVELS]; + union { /* Color */ struct { @@ -215,9 +218,6 @@ struct gfx9_surf_layout { uint32_t dcc_retile_num_elements; void *dcc_retile_map; - /* DCC level info */ - struct gfx9_surf_level dcc_levels[RADEON_SURF_MAX_LEVELS]; - /* CMASK level info (only level 0) */ struct gfx9_surf_level cmask_level0; }; @@ -227,9 +227,6 @@ struct gfx9_surf_layout { uint64_t stencil_offset; /* separate stencil */ uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */ uint8_t stencil_swizzle_mode; - - /* HTILE level info */ - struct gfx9_surf_level htile_levels[RADEON_SURF_MAX_LEVELS]; }; }; }; diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 17eb1428025..ce5dce8de6e 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1282,8 +1282,8 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { /* DCC for mipmaps+layers is currently disabled. */ offset += image->planes[0].surface.dcc_slice_size * range->baseArrayLayer + - image->planes[0].surface.u.gfx9.dcc_levels[level].offset; - size = image->planes[0].surface.u.gfx9.dcc_levels[level].size * layer_count; + image->planes[0].surface.u.gfx9.meta_levels[level].offset; + size = image->planes[0].surface.u.gfx9.meta_levels[level].size * layer_count; } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { /* Mipmap levels and layers aren't implemented. */ assert(level == 0); @@ -1330,8 +1330,8 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im for (uint32_t l = 0; l < level_count; l++) { uint32_t level = range->baseMipLevel + l; uint64_t offset = image->offset + image->planes[0].surface.htile_offset + - image->planes[0].surface.u.gfx9.htile_levels[level].offset; - uint32_t size = image->planes[0].surface.u.gfx9.htile_levels[level].size; + image->planes[0].surface.u.gfx9.meta_levels[level].offset; + uint32_t size = image->planes[0].surface.u.gfx9.meta_levels[level].size; /* Do not clear this level if it can be compressed. */ if (!size) _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
