Module: Mesa Branch: master Commit: 48dbdc62bf8611c60a7c27ece9b7c5ba11212e46 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=48dbdc62bf8611c60a7c27ece9b7c5ba11212e46
Author: Marek Olšák <marek.ol...@amd.com> Date: Fri Apr 2 13:33:38 2021 -0400 ac/surface: change legacy_surf_level::offset to 32-bit offset_256B shifted by 8 Images are always aligned to 256B (enforced by register and descriptor fields) and limited to 40-bit addresses. This saves some space. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-pra...@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083> --- src/amd/common/ac_surface.c | 12 +++++------ src/amd/common/ac_surface.h | 2 +- src/amd/vulkan/radv_device.c | 8 ++++---- src/amd/vulkan/radv_formats.c | 4 ++-- src/amd/vulkan/radv_image.c | 4 ++-- src/gallium/drivers/r600/evergreen_state.c | 24 +++++++++++----------- src/gallium/drivers/r600/r600_state.c | 22 ++++++++++---------- src/gallium/drivers/r600/r600_texture.c | 12 +++++------ src/gallium/drivers/r600/radeon_uvd.c | 2 +- src/gallium/drivers/r600/radeon_video.c | 2 +- src/gallium/drivers/radeon/radeon_uvd.c | 2 +- src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 4 ++-- src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 4 ++-- src/gallium/drivers/radeon/radeon_vce_50.c | 4 ++-- src/gallium/drivers/radeon/radeon_vce_52.c | 4 ++-- src/gallium/drivers/radeonsi/si_descriptors.c | 2 +- src/gallium/drivers/radeonsi/si_state.c | 6 +++--- src/gallium/drivers/radeonsi/si_texture.c | 8 ++++---- src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 4 ++-- 19 files changed, 65 insertions(+), 65 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index b47159f3b04..23ef5381e76 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -797,7 +797,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config * surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level]; dcc_level = &surf->u.legacy.dcc_level[level]; - surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); + surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256; surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4; surf_level->nblk_x = AddrSurfInfoOut->pitch; surf_level->nblk_y = AddrSurfInfoOut->height; @@ -835,7 +835,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config * } } - surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize; + surf->surf_size = (uint64_t)surf_level->offset_256B * 256 + AddrSurfInfoOut->surfSize; /* Clear DCC fields at the beginning. */ if (!AddrSurfInfoIn->flags.depth && !AddrSurfInfoIn->flags.stencil) @@ -2721,7 +2721,7 @@ bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_s if (info->chip_class >= GFX9) offset = surf->u.gfx9.surf_offset; else - offset = surf->u.legacy.level[0].offset; + offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256; if (offset || /* Non-zero planes ignore metadata. */ size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */ @@ -2851,7 +2851,7 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_s /* Dwords [10:..] contain the mipmap level offsets. */ if (info->chip_class <= GFX8) { for (unsigned i = 0; i < num_mipmap_levels; i++) - metadata[10 + i] = surf->u.legacy.level[i].offset >> 8; + metadata[10 + i] = surf->u.legacy.level[i].offset_256B; *size_metadata += num_mipmap_levels * 4; } @@ -2927,7 +2927,7 @@ bool ac_surface_override_offset_stride(const struct radeon_info *info, struct ra if (offset) { for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i) - surf->u.legacy.level[i].offset += offset; + surf->u.legacy.level[i].offset_256B += offset / 256; } } @@ -2970,7 +2970,7 @@ uint64_t ac_surface_get_plane_offset(enum chip_class chip_class, return surf->u.gfx9.surf_offset + layer * surf->u.gfx9.surf_slice_size; } else { - return surf->u.legacy.level[0].offset + + return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 + layer * (uint64_t)surf->u.legacy.level[0].slice_size_dw * 4; } case 1: diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 7438c5ee7ad..f5a8508d85e 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -85,7 +85,7 @@ enum radeon_micro_mode #define RADEON_SURF_PRT (1ull << 32) struct legacy_surf_level { - uint64_t offset; + uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ unsigned nblk_x : 15; unsigned nblk_y : 15; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 2800de4384d..0120a6e05f2 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -4140,7 +4140,7 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem offset = surface->u.gfx9.surf_slice_size * layer + surface->u.gfx9.prt_level_offset[level]; pitch = surface->u.gfx9.prt_level_pitch[level]; } else { - offset = surface->u.legacy.level[level].offset + + offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 + surface->u.legacy.level[level].slice_size_dw * 4 * layer; pitch = surface->u.legacy.level[level].nblk_x; } @@ -6322,7 +6322,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; unsigned pitch_tile_max, slice_tile_max, tile_mode_index; - cb->cb_color_base += level_info->offset >> 8; + cb->cb_color_base += level_info->offset_256B; if (level_info->mode == RADEON_SURF_MODE_2D) cb->cb_color_base |= surf->tile_swizzle; @@ -6633,8 +6633,8 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf if (stencil_only) level_info = &surf->u.legacy.stencil_level[level]; - z_offs += surf->u.legacy.level[level].offset; - s_offs += surf->u.legacy.stencil_level[level].offset; + z_offs += (uint64_t)surf->u.legacy.level[level].offset_256B * 256; + s_offs += (uint64_t)surf->u.legacy.stencil_level[level].offset_256B * 256; ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image)); ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1); diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index 925444d3fd0..5770e2789bb 100644 --- a/src/amd/vulkan/radv_formats.c +++ b/src/amd/vulkan/radv_formats.c @@ -1814,9 +1814,9 @@ radv_GetImageSparseMemoryRequirements2(VkDevice _device, image->planes[0].surface.u.gfx9.surf_slice_size; } else { req->memoryRequirements.imageMipTailOffset = - image->planes[0] + (uint64_t)image->planes[0] .surface.u.legacy.level[req->memoryRequirements.imageMipTailFirstLod] - .offset; + .offset_256B * 256; req->memoryRequirements.imageMipTailSize = image->size - req->memoryRequirements.imageMipTailOffset; req->memoryRequirements.imageMipTailStride = 0; diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index eb3b9ac47de..94a380d22ed 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -688,7 +688,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im else va += plane->surface.u.gfx9.surf_offset; } else - va += base_level_info->offset; + va += (uint64_t)base_level_info->offset_256B * 256; state[0] = va >> 8; if (chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D) @@ -2126,7 +2126,7 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image, if (image->type == VK_IMAGE_TYPE_3D) pLayout->size *= u_minify(image->info.depth, level); } else { - pLayout->offset = surface->u.legacy.level[level].offset + + pLayout->offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer; pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe; pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4; diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index dce4b5c33f0..f9340baa6e8 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -847,7 +847,7 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx, tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) | S_030004_TEX_DEPTH(depth - 1) | S_030004_ARRAY_MODE(array_mode)); - tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8; + tex_resource_words[2] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8; *skip_mip_address_reloc = false; /* TEX_RESOURCE_WORD3.MIP_ADDRESS */ @@ -861,9 +861,9 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx, tex_resource_words[3] = (tmp->fmask.offset + va) >> 8; } } else if (last_level && texture->nr_samples <= 1) { - tex_resource_words[3] = (surflevel[1].offset + va) >> 8; + tex_resource_words[3] = ((uint64_t)surflevel[1].offset_256B * 256 + va) >> 8; } else { - tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8; + tex_resource_words[3] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8; } last_layer = params->last_layer; @@ -1124,7 +1124,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx, bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE; int i; - color->offset = rtex->surface.u.legacy.level[level].offset; + color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; color->view = S_028C6C_SLICE_START(first_layer) | S_028C6C_SLICE_MAX(last_layer); @@ -1361,7 +1361,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, assert(format != ~0); offset = rtex->resource.gpu_address; - offset += rtex->surface.u.legacy.level[level].offset; + offset += (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; switch (rtex->surface.u.legacy.level[level].mode) { case RADEON_SURF_MODE_2D: @@ -1411,7 +1411,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, stile_split = eg_tile_split(stile_split); - stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset; + stencil_offset = (uint64_t)rtex->surface.u.legacy.stencil_level[level].offset_256B * 256; stencil_offset += rtex->resource.gpu_address; surf->db_stencil_base = stencil_offset >> 8; @@ -3813,8 +3813,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, x = src_x; y = src_y; z = src_z; - base = rsrc->surface.u.legacy.level[src_level].offset; - addr = rdst->surface.u.legacy.level[dst_level].offset; + base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; + addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; addr += dst_y * pitch + dst_x * bpp; bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh); @@ -3838,8 +3838,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, x = dst_x; y = dst_y; z = dst_z; - base = rdst->surface.u.legacy.level[dst_level].offset; - addr = rsrc->surface.u.legacy.level[src_level].offset; + base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; + addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z; addr += src_y * pitch + src_x * bpp; bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh); @@ -3961,10 +3961,10 @@ static void evergreen_dma_copy(struct pipe_context *ctx, * dst_x/y == 0 * dst_pitch == src_pitch */ - src_offset= rsrc->surface.u.legacy.level[src_level].offset; + src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z; src_offset += src_y * src_pitch + src_x * bpp; - dst_offset = rdst->surface.u.legacy.level[dst_level].offset; + dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; dst_offset += dst_y * dst_pitch + dst_x * bpp; evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 56796244cfd..6eb2bd42b1c 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -755,11 +755,11 @@ r600_create_sampler_view_custom(struct pipe_context *ctx, view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) | S_038004_TEX_DEPTH(depth - 1) | S_038004_DATA_FORMAT(format)); - view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset >> 8; + view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B; if (offset_level >= tmp->resource.b.b.last_level) { - view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset >> 8; + view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B; } else { - view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset >> 8; + view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B; } view->tex_resource_words[4] = (word4 | S_038010_REQUEST_SIZE(1) | @@ -824,7 +824,7 @@ static void r600_init_color_surface(struct r600_context *rctx, assert(rtex); } - offset = rtex->surface.u.legacy.level[level].offset; + offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | S_028080_SLICE_MAX(surf->base.u.tex.last_layer); @@ -1041,7 +1041,7 @@ static void r600_init_depth_surface(struct r600_context *rctx, unsigned level, pitch, slice, format, offset, array_mode; level = surf->base.u.tex.level; - offset = rtex->surface.u.legacy.level[level].offset; + offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; if (slice) { @@ -2884,8 +2884,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, x = src_x; y = src_y; z = src_z; - base = rsrc->surface.u.legacy.level[src_level].offset; - addr = rdst->surface.u.legacy.level[dst_level].offset; + base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; + addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; addr += dst_y * pitch + dst_x * bpp; } else { @@ -2903,8 +2903,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, x = dst_x; y = dst_y; z = dst_z; - base = rdst->surface.u.legacy.level[dst_level].offset; - addr = rsrc->surface.u.legacy.level[src_level].offset; + base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; + addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z; addr += src_y * pitch + src_x * bpp; } @@ -3007,10 +3007,10 @@ static void r600_dma_copy(struct pipe_context *ctx, * dst_x/y == 0 * dst_pitch == src_pitch */ - src_offset= rsrc->surface.u.legacy.level[src_level].offset; + src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z; src_offset += src_y * src_pitch + src_x * bpp; - dst_offset = rdst->surface.u.legacy.level[dst_level].offset; + dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; dst_offset += dst_y * dst_pitch + dst_x * bpp; size = src_box->height * src_pitch; diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index afa44af5d2b..7f461ac051a 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -183,11 +183,11 @@ static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen, *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4; if (!box) - return rtex->surface.u.legacy.level[level].offset; + return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; /* Each texture is an array of mipmap levels. Each level is * an array of slices. */ - return rtex->surface.u.legacy.level[level].offset + + return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 + box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 + (box->y / rtex->surface.blk_h * rtex->surface.u.legacy.level[level].nblk_x + @@ -262,7 +262,7 @@ static int r600_init_surface(struct r600_common_screen *rscreen, if (offset) { for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i) - surface->u.legacy.level[i].offset += offset; + surface->u.legacy.level[i].offset_256B += offset / 256; } return 0; @@ -455,7 +455,7 @@ static void r600_texture_get_info(struct pipe_screen* screen, return; if (resource->target != PIPE_BUFFER) { - offset = rtex->surface.u.legacy.level[0].offset; + offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256; stride = rtex->surface.u.legacy.level[0].nblk_x * rtex->surface.bpe; } @@ -868,7 +868,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen, u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", " "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " "mode=%u, tiling_index = %u\n", - i, rtex->surface.u.legacy.level[i].offset, + i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256, (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4, u_minify(rtex->resource.b.b.width0, i), u_minify(rtex->resource.b.b.height0, i), @@ -886,7 +886,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen, "slice_size=%"PRIu64", npix_x=%u, " "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " "mode=%u, tiling_index = %u\n", - i, rtex->surface.u.legacy.stencil_level[i].offset, + i, (uint64_t)rtex->surface.u.legacy.stencil_level[i].offset_256B * 256, (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4, u_minify(rtex->resource.b.b.width0, i), u_minify(rtex->resource.b.b.height0, i), diff --git a/src/gallium/drivers/r600/radeon_uvd.c b/src/gallium/drivers/r600/radeon_uvd.c index 4d0e0bf83c3..fa22ba586ae 100644 --- a/src/gallium/drivers/r600/radeon_uvd.c +++ b/src/gallium/drivers/r600/radeon_uvd.c @@ -1170,7 +1170,7 @@ error: /* calculate top/bottom offset */ static unsigned texture_offset(struct radeon_surf *surface, unsigned layer) { - return surface->u.legacy.level[0].offset + + return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 + layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4; } diff --git a/src/gallium/drivers/r600/radeon_video.c b/src/gallium/drivers/r600/radeon_video.c index a49c0a0120d..1ebb8708de4 100644 --- a/src/gallium/drivers/r600/radeon_video.c +++ b/src/gallium/drivers/r600/radeon_video.c @@ -180,7 +180,7 @@ void rvid_join_surfaces(struct r600_common_context *rctx, surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split; for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j) - surfaces[i]->u.legacy.level[j].offset += off; + surfaces[i]->u.legacy.level[j].offset_256B += off / 256; off += surfaces[i]->surf_size; } diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 612cb18f34c..ec7d8b5ff19 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -1379,7 +1379,7 @@ static unsigned texture_offset(struct radeon_surf *surface, unsigned layer, switch (type) { default: case RUVD_SURFACE_TYPE_LEGACY: - return surface->u.legacy.level[0].offset + + return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 + layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4; break; case RUVD_SURFACE_TYPE_GFX9: diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c index e90fecd595f..b76d2dc6a4e 100644 --- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c +++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c @@ -898,8 +898,8 @@ static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc) RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size); if (sscreen->info.chip_class < GFX9) { - RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.legacy.level[0].offset); - RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.legacy.level[0].offset); + RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); + RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); } else { RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c index ee7cf15e1e6..30b43536c4a 100644 --- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c +++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c @@ -308,9 +308,9 @@ static void encode(struct rvce_encoder *enc) RVCE_CS(0x00000000); // endOfSequence RVCE_CS(0x00000000); // endOfStream RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, - enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo + (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, - enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo + (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c b/src/gallium/drivers/radeon/radeon_vce_50.c index 591207c6f96..e75ceec5950 100644 --- a/src/gallium/drivers/radeon/radeon_vce_50.c +++ b/src/gallium/drivers/radeon/radeon_vce_50.c @@ -118,9 +118,9 @@ static void encode(struct rvce_encoder *enc) RVCE_CS(0x00000000); // endOfSequence RVCE_CS(0x00000000); // endOfStream RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, - enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo + (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, - enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo + (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c b/src/gallium/drivers/radeon/radeon_vce_52.c index ea1ccec00b8..f70534d14be 100644 --- a/src/gallium/drivers/radeon/radeon_vce_52.c +++ b/src/gallium/drivers/radeon/radeon_vce_52.c @@ -263,9 +263,9 @@ static void encode(struct rvce_encoder *enc) if (sscreen->info.chip_class < GFX9) { RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, - enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo + (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, - enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo + (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index ba7bd9e6ea3..0e4dc81de40 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -314,7 +314,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture else va += tex->surface.u.gfx9.surf_offset; } else { - va += base_level_info->offset; + va += (uint64_t)base_level_info->offset_256B * 256; } state[0] = va >> 8; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index c09e0ed6fb1..1113e4ad54a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2506,9 +2506,9 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); surf->db_depth_base = - (tex->buffer.gpu_address + tex->surface.u.legacy.level[level].offset) >> 8; + (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B; surf->db_stencil_base = - (tex->buffer.gpu_address + tex->surface.u.legacy.stencil_level[level].offset) >> 8; + (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.stencil_level[level].offset_256B; z_info = S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)); @@ -3127,7 +3127,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) unsigned pitch_tile_max, slice_tile_max, tile_mode_index; unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice; - cb_color_base += level_info->offset >> 8; + cb_color_base += level_info->offset_256B; /* Only macrotiled modes can set tile swizzle. */ if (level_info->mode == RADEON_SURF_MODE_2D) cb_color_base |= tex->surface.tile_swizzle; diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 30f2cea12e4..ce750fe3d90 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -142,11 +142,11 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_textu *layer_stride = (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4; if (!box) - return tex->surface.u.legacy.level[level].offset; + return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256; /* Each texture is an array of mipmap levels. Each level is * an array of slices. */ - return tex->surface.u.legacy.level[level].offset + + return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256 + box->z * (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 + (box->y / tex->surface.blk_h * tex->surface.u.legacy.level[level].nblk_x + box->x / tex->surface.blk_w) * @@ -846,7 +846,7 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, " Level[%i]: offset=%" PRIu64 ", slice_size=%" PRIu64 ", " "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " "mode=%u, tiling_index = %u\n", - i, tex->surface.u.legacy.level[i].offset, + i, (uint64_t)tex->surface.u.legacy.level[i].offset_256B * 256, (uint64_t)tex->surface.u.legacy.level[i].slice_size_dw * 4, u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i), u_minify(tex->buffer.b.b.depth0, i), tex->surface.u.legacy.level[i].nblk_x, @@ -860,7 +860,7 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, "slice_size=%" PRIu64 ", npix_x=%u, " "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " "mode=%u, tiling_index = %u\n", - i, tex->surface.u.legacy.stencil_level[i].offset, + i, (uint64_t)tex->surface.u.legacy.stencil_level[i].offset_256B * 256, (uint64_t)tex->surface.u.legacy.stencil_level[i].slice_size_dw * 4, u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i), u_minify(tex->buffer.b.b.depth0, i), diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index 505bb89751b..00961ea1d7e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -67,7 +67,7 @@ static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm, const struct legacy_surf_level *level_ws, unsigned bpe) { - level_drm->offset = level_ws->offset; + level_drm->offset = (uint64_t)level_ws->offset_256B * 256; level_drm->slice_size = (uint64_t)level_ws->slice_size_dw * 4; level_drm->nblk_x = level_ws->nblk_x; level_drm->nblk_y = level_ws->nblk_y; @@ -79,7 +79,7 @@ static void surf_level_drm_to_winsys(struct legacy_surf_level *level_ws, const struct radeon_surface_level *level_drm, unsigned bpe) { - level_ws->offset = level_drm->offset; + level_ws->offset_256B = level_drm->offset / 256; level_ws->slice_size_dw = level_drm->slice_size / 4; level_ws->nblk_x = level_drm->nblk_x; level_ws->nblk_y = level_drm->nblk_y; _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit