URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9b527a9a501bf15c33957ac7ae431d996aea606
Author: Marek Olšák <[email protected]>
Date: Sun Apr 4 20:19:55 2021 -0400
radeonsi: unify internal compute with SSBOs in si_launch_grid_internal_ssbos
just deduplicate the code
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec605260354a884361e726bf5de22d56e505a388
Author: Marek Olšák <[email protected]>
Date: Sun Apr 4 19:37:01 2021 -0400
radeonsi: move binding the internal compute shader into
si_launch_grid_internal
instead of doing it in each function
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa8a6e5f26a5722c614407b2c43bad64d0dc8fee
Author: Marek Olšák <[email protected]>
Date: Sun Apr 4 17:01:01 2021 -0400
radeonsi: enable DCC for MSAA 4x and 8x on gfx9
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3120113ee77621964bb009f9cbd13488b087e734
Author: Marek Olšák <[email protected]>
Date: Sun Apr 4 16:58:29 2021 -0400
radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9
MSAA 4x and 8x should only clear the first 2 samples because other samples
are uncompressed. The compute shader only clears that subset of DCC.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b95f51ef139b9995da020c19340410340f959db
Author: Marek Olšák <[email protected]>
Date: Fri Mar 19 16:14:23 2021 -0400
radeonsi: fix and enable full DCC with MSAA 2x on gfx9
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e68fae25f6e5416787edb8dd74844f4c89ff482
Author: Marek Olšák <[email protected]>
Date: Mon Mar 22 19:43:53 2021 -0400
ac,radeonsi: rewrite DCC retiling without the DCC retile map
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.
The RADV code is disabled.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35adf91de7c2ba310fd851ea0b437b27def9b280
Author: Marek Olšák <[email protected]>
Date: Mon Mar 22 21:21:30 2021 -0400
ac/surface: limit the number of swizzle modes that can have displayable DCC
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ce8c440dd7a1137c6bda95b3623921e7983c7a4
Author: Marek Olšák <[email protected]>
Date: Fri Mar 19 15:52:44 2021 -0400
ac/surface: add a test of DccAddrFromCoord prototype outside of addrlib
The test takes over 2 minutes on a 12C/24T CPU with OpenMP.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd2832ee5107201493d59f70983f162653e53c7d
Author: Marek Olšák <[email protected]>
Date: Mon Apr 5 14:01:37 2021 -0400
meson: add an optional OpenMP dependency for AMD tests
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Acked-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df2cbdd2e321d198e973be21eea25e9b296cceff
Author: Marek Olšák <[email protected]>
Date: Fri Mar 19 15:51:36 2021 -0400
amd/addrlib: expose DCC address equations to drivers
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8771d45a741da6c6b764826a95f99e453e7afeb9
Author: Marek Olšák <[email protected]>
Date: Wed Apr 7 17:20:53 2021 -0400
ac/surface/tests: fix a random segfault in the modifier test
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=23b2cf032ae733844693a0f67079e3414178510f
Author: Marek Olšák <[email protected]>
Date: Fri Mar 19 16:05:40 2021 -0400
ac/surface/tests: test Sienna Cichlid and Navy Flounder
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b3dbde3b9d4773a07a2de9c5bdb223c6e8cf3a9
Author: Marek Olšák <[email protected]>
Date: Wed Mar 31 07:58:28 2021 -0400
ac/surface: only apply the 3D swizzle mode tuning to gfx10+
This fixes an addrlib failure on gfx9.
Fixes: b43f40166cd "ac/surface: select best swizzle mode for 3D sampler
performance"
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec42f52013bb025e539e508ee9a47ea5ba0f1945
Author: Marek Olšák <[email protected]>
Date: Tue Mar 23 22:53:00 2021 -0400
radeonsi: allow DCC_DECOMPRESS via CB with MSAA textures
The shader-based codepath doesn't support it.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8277732358d426a9076892172231dce3d7b53edb
Author: Marek Olšák <[email protected]>
Date: Wed Mar 31 06:50:14 2021 -0400
radeonsi: try to fix DCC coherency issues with DCC decompression
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7c58559f5731790f4e68f1b1cb38c10818efa96
Author: Marek Olšák <[email protected]>
Date: Mon Mar 29 02:24:39 2021 -0400
radeonsi: refine fast clears for small buffers, always use them for large
HTILE
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06b6af596c2d73410469733d6ef6fe88a3b7248c
Author: Marek Olšák <[email protected]>
Date: Sun Mar 21 16:57:15 2021 -0400
radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW
This adds a clear_buffer compute shader that does read-modify-write to
update a subset of bits in HTILE.
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84fa21a611b6b80e6effc3aa1df902e49a563500
Author: Marek Olšák <[email protected]>
Date: Sun Mar 21 12:17:17 2021 -0400
radeonsi: when transitioning to TC-compat HTILE, try to do a proper clear
instead of always clearing to uncompressed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=558ab3310d5c05b4fe3ea93f7b58c67891dc9c44
Author: Marek Olšák <[email protected]>
Date: Sun Mar 21 12:01:04 2021 -0400
radeonsi: enable DCC fast clears for non-zero mipmap levels and 0/1 clear
values
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9defe8aca953b69615728c84d8ff6ed51bdded00
Author: Marek Olšák <[email protected]>
Date: Sun Mar 21 03:43:44 2021 -0400
radeonsi: implement fast Z/S clears using clear_buffer on HTILE
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2714d5dd4d61119e2d95cc7778e3a026fd7115d
Author: Marek Olšák <[email protected]>
Date: Sun Mar 21 03:41:59 2021 -0400
radeonsi: indent the code for TC-compatibility HTILE transition
So that HTILE clears can be nicely inserted into a new else statement there.
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcd01ad4448ccd7bd587a0531e8a968e7eee6029
Author: Marek Olšák <[email protected]>
Date: Sun Mar 21 03:12:21 2021 -0400
radeonsi: add si_can_fast_clear_depth/stencil helpers
for later use
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4dd8d58ad5dbd3be0c2fa5520c78248ef15e30dd
Author: Marek Olšák <[email protected]>
Date: Sun Mar 21 00:17:44 2021 -0400
radeonsi: clean up some mess around htile_stencil_disabled
Set the final value in si_texture_create_object, so that other places
don't have to derive it redundantly.
The only thing to remember is that HTILE stencil can be enabled when
stencil is not present, and it can be disabled when stencil is present
due to various workarounds.
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcd1a69f793ecac052c9c796d9e30489f212500b
Author: Marek Olšák <[email protected]>
Date: Sat Mar 20 20:29:33 2021 -0400
radeonsi: parallelize Z/S conversion into TC-compatible with fast color
clears
It's not really a fast clear, but it's the next logical step towards doing
HTILE clears here.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb72d41b1855c61479e091c6af5927b8515ecf9b
Author: Marek Olšák <[email protected]>
Date: Sat Mar 20 19:59:06 2021 -0400
radeonsi: implement Z/S fast clear for non-zero mipmap levels
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6434b0b652d1e8f73766a67005ec977e8ec922e5
Author: Marek Olšák <[email protected]>
Date: Fri Mar 19 20:47:48 2021 -0400
radeonsi: implement per-level DCC and CMASK fast clears for gfx10+
Fast clears are only used for level 0. This enables clearing level 0
of CMASK and DCC on gfx10+ when there are multiple mipmap levels.
vi_dcc_clear_level can also clear any level now.
Mipmapped array textures are still cleared slowly.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=059f042fb1d24daf9138b3b0d7fbcd869dc4255a
Author: Marek Olšák <[email protected]>
Date: Fri Mar 19 19:05:13 2021 -0400
radeonsi: allow trivial DCC clears for shared textures with DCC constant
encode
This relaxes the existing restriction.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c00b314ae4835542f068273ae920963d8809d326
Author: Marek Olšák <[email protected]>
Date: Wed Mar 17 22:11:19 2021 -0400
radeonsi: restructure DCC disablement into a switch
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa43d619531778fbb36e19f9a989a8b4b284121b
Author: Marek Olšák <[email protected]>
Date: Mon Mar 15 22:17:39 2021 -0400
radeonsi: don't cache FMASK transactions from CB in L2
FMASK is usually pretty large. It's better to leave the cache to shaders.
FMASK stores are still cached, but they can be evicted sooner, which is
the same as other color stores. Only DCC, HTILE, and CMASK are cached.
I haven't benchmarked this, but it seems like the right thing to do.
This only affected APUs.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
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