Module: Mesa Branch: staging/21.1 Commit: f4b2cde0c4dce7f9c5df340119ec73cfda017279 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4b2cde0c4dce7f9c5df340119ec73cfda017279
Author: Danylo Piliaiev <[email protected]> Date: Mon Feb 15 15:53:46 2021 +0200 ir3: memory_barrier also controls shared memory access order nir_intrinsic_memory_barrier has the same semantic as memoryBarrier() in GLSL, which is: GLSL 4.60, 4.10. "Memory Qualifiers": "The built-in function memoryBarrier() can be used if needed to guarantee the completion and relative ordering of memory accesses performed by a single shader invocation." GLSL 4.60, 8.17. "Shader Memory Control Functions": "The built-in functions memoryBarrier() and groupMemoryBarrier() wait for the completion of accesses to all of the above variable types." Fixes tests: dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp Fixes: 819a613a ("freedreno/ir3: moar better scheduler") Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054> (cherry picked from commit cb8a00791cc9618f5be903c31abf737b42e4cf46) --- .pick_status.json | 2 +- src/freedreno/ci/deqp-freedreno-a630-fails.txt | 2 -- src/freedreno/ir3/ir3.h | 2 +- src/freedreno/ir3/ir3_compiler_nir.c | 13 +------------ 4 files changed, 3 insertions(+), 16 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 3ec2cee5e12..19220ee582e 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -211,7 +211,7 @@ "description": "ir3: memory_barrier also controls shared memory access order", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "819a613ae33410584e13e78e78af82c71716f67d" }, diff --git a/src/freedreno/ci/deqp-freedreno-a630-fails.txt b/src/freedreno/ci/deqp-freedreno-a630-fails.txt index f3639f35712..fb130509949 100644 --- a/src/freedreno/ci/deqp-freedreno-a630-fails.txt +++ b/src/freedreno/ci/deqp-freedreno-a630-fails.txt @@ -129,8 +129,6 @@ dEQP-VK.image.subresource_layout.3d.all_levels.r16g16b16a16_snorm,Fail dEQP-VK.image.subresource_layout.3d.all_levels.r8_snorm,Fail dEQP-VK.image.subresource_layout.3d.all_levels.r8g8b8a8_snorm,Fail dEQP-VK.info.device_mandatory_features,Fail -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp,Fail -dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp,Fail dEQP-VK.pipeline.extended_dynamic_state.after_pipelines.depth_compare_always_greater,Fail dEQP-VK.pipeline.extended_dynamic_state.after_pipelines.depth_compare_greater,Fail dEQP-VK.pipeline.extended_dynamic_state.after_pipelines.depth_compare_greater_equal_greater,Fail diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index bc11f89b94b..eaabef6c5bd 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -392,7 +392,7 @@ struct ir3_instruction { * shared image atomic SSBO everything * barrier()/ - R/W R/W R/W R/W X * groupMemoryBarrier() - * memoryBarrier() - R/W R/W + * memoryBarrier() * (but only images declared coherent?) * memoryBarrierAtomic() - R/W * memoryBarrierBuffer() - R/W diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 4db7e87cb14..14754036a24 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1312,18 +1312,6 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr) barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY; barrier->barrier_class = IR3_BARRIER_EVERYTHING; break; - case nir_intrinsic_memory_barrier: - barrier = ir3_FENCE(b); - barrier->cat7.g = true; - barrier->cat7.r = true; - barrier->cat7.w = true; - barrier->cat7.l = true; - barrier->barrier_class = IR3_BARRIER_IMAGE_W | - IR3_BARRIER_BUFFER_W; - barrier->barrier_conflict = - IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W | - IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; - break; case nir_intrinsic_memory_barrier_buffer: barrier = ir3_FENCE(b); barrier->cat7.g = true; @@ -1353,6 +1341,7 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr) barrier->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W; break; + case nir_intrinsic_memory_barrier: case nir_intrinsic_group_memory_barrier: barrier = ir3_FENCE(b); barrier->cat7.g = true; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
