Module: Mesa Branch: main Commit: 733c9b6d17f65e3c282e550fc0445d0ae27e7e14 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=733c9b6d17f65e3c282e550fc0445d0ae27e7e14
Author: Bas Nieuwenhuizen <[email protected]> Date: Mon Mar 22 01:25:19 2021 +0100 radv: Add RT pipeline bind. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767> --- src/amd/vulkan/radv_cmd_buffer.c | 18 ++++++++++++++---- src/amd/vulkan/radv_private.h | 1 + 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 8c0977e9080..41dfb511d86 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4338,6 +4338,17 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline cmd_buffer->state.compute_pipeline = pipeline; cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT; break; + case VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR: + if (cmd_buffer->state.rt_pipeline == pipeline) + return; + radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint); + + cmd_buffer->state.rt_pipeline = pipeline; + cmd_buffer->push_constant_stages |= + (VK_SHADER_STAGE_RAYGEN_BIT_KHR | VK_SHADER_STAGE_ANY_HIT_BIT_KHR | + VK_SHADER_STAGE_CLOSEST_HIT_BIT_KHR | VK_SHADER_STAGE_MISS_BIT_KHR | + VK_SHADER_STAGE_INTERSECTION_BIT_KHR | VK_SHADER_STAGE_CALLABLE_BIT_KHR); + break; case VK_PIPELINE_BIND_POINT_GRAPHICS: if (cmd_buffer->state.pipeline == pipeline) return; @@ -5800,10 +5811,9 @@ struct radv_dispatch_info { }; static void -radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, +radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline, const struct radv_dispatch_info *info) { - struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE]; unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator; struct radeon_winsys *ws = cmd_buffer->device->ws; @@ -5959,7 +5969,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf radv_upload_compute_shader_descriptors(cmd_buffer, pipeline, bind_point); - radv_emit_dispatch_packets(cmd_buffer, info); + radv_emit_dispatch_packets(cmd_buffer, pipeline, info); /* <-- CUs are busy here --> */ /* Start prefetches after the dispatch has been started. Both @@ -5982,7 +5992,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf radv_upload_compute_shader_descriptors(cmd_buffer, pipeline, bind_point); radv_emit_compute_pipeline(cmd_buffer, pipeline); - radv_emit_dispatch_packets(cmd_buffer, info); + radv_emit_dispatch_packets(cmd_buffer, pipeline, info); } if (pipeline_is_dirty) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 7a23edd6ea5..ee672204efa 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1338,6 +1338,7 @@ struct radv_cmd_state { struct radv_pipeline *emitted_pipeline; struct radv_pipeline *compute_pipeline; struct radv_pipeline *emitted_compute_pipeline; + struct radv_pipeline *rt_pipeline; /* emitted = emitted_compute_pipeline */ struct radv_framebuffer *framebuffer; struct radv_render_pass *pass; const struct radv_subpass *subpass; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
