Module: Mesa Branch: main Commit: c7904b5b9b6e24dfa9bee9d6104dc1230738ab4f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7904b5b9b6e24dfa9bee9d6104dc1230738ab4f
Author: Bas Nieuwenhuizen <[email protected]> Date: Tue Apr 6 11:33:38 2021 +0200 aco: Implement bvh64_intersect_ray_amd intrinsic. Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10818> --- src/amd/compiler/aco_assembler.cpp | 3 +- src/amd/compiler/aco_instruction_selection.cpp | 36 ++++++++++++++++++++++ .../compiler/aco_instruction_selection_setup.cpp | 1 + src/amd/compiler/aco_opcodes.py | 1 + 4 files changed, 40 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp index 19b63d12752..ce42f59a659 100644 --- a/src/amd/compiler/aco_assembler.cpp +++ b/src/amd/compiler/aco_assembler.cpp @@ -427,7 +427,8 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* MIMG_instruction& mimg = instr->mimg(); uint32_t encoding = (0b111100 << 26); encoding |= mimg.slc ? 1 << 25 : 0; - encoding |= opcode << 18; + encoding |= (opcode & 0x7f) << 18; + encoding |= (opcode >> 7) & 1; encoding |= mimg.lwe ? 1 << 17 : 0; encoding |= mimg.tfe ? 1 << 16 : 0; encoding |= mimg.glc ? 1 << 13 : 0; diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 0794ca3596a..496dafb3eef 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5598,6 +5598,39 @@ static MIMG_instruction *emit_mimg(Builder& bld, aco_opcode op, return res; } +void visit_bvh64_intersect_ray_amd(isel_context *ctx, nir_intrinsic_instr *instr) +{ + Builder bld(ctx->program, ctx->block); + Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); + Temp resource = get_ssa_temp(ctx, instr->src[0].ssa); + Temp node = get_ssa_temp(ctx, instr->src[1].ssa); + Temp tmax = get_ssa_temp(ctx, instr->src[2].ssa); + Temp origin = get_ssa_temp(ctx, instr->src[3].ssa); + Temp dir = get_ssa_temp(ctx, instr->src[4].ssa); + Temp inv_dir = get_ssa_temp(ctx, instr->src[5].ssa); + + std::vector<Temp> args; + args.push_back(emit_extract_vector(ctx, node, 0, v1)); + args.push_back(emit_extract_vector(ctx, node, 1, v1)); + args.push_back(as_vgpr(ctx, tmax)); + args.push_back(emit_extract_vector(ctx, origin, 0, v1)); + args.push_back(emit_extract_vector(ctx, origin, 1, v1)); + args.push_back(emit_extract_vector(ctx, origin, 2, v1)); + args.push_back(emit_extract_vector(ctx, dir, 0, v1)); + args.push_back(emit_extract_vector(ctx, dir, 1, v1)); + args.push_back(emit_extract_vector(ctx, dir, 2, v1)); + args.push_back(emit_extract_vector(ctx, inv_dir, 0, v1)); + args.push_back(emit_extract_vector(ctx, inv_dir, 1, v1)); + args.push_back(emit_extract_vector(ctx, inv_dir, 2, v1)); + + MIMG_instruction *mimg = emit_mimg(bld, aco_opcode::image_bvh64_intersect_ray, + Definition(dst), resource, Operand(s4), args); + mimg->dim = ac_image_1d; + mimg->dmask = 0xf; + mimg->unrm = true; + mimg->r128 = true; +} + /* Adjust the sample index according to FMASK. * * For uncompressed MSAA surfaces, FMASK should return 0x76543210, @@ -8515,6 +8548,9 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) case nir_intrinsic_load_sbt_amd: visit_load_sbt_amd(ctx, instr); break; + case nir_intrinsic_bvh64_intersect_ray_amd: + visit_bvh64_intersect_ray_amd(ctx, instr); + break; default: isel_err(&instr->instr, "Unimplemented intrinsic instr"); abort(); diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 1e544a98787..9c3dde645f5 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -805,6 +805,7 @@ void init_context(isel_context *ctx, nir_shader *shader) case nir_intrinsic_load_packed_passthrough_primitive_amd: case nir_intrinsic_gds_atomic_add_amd: case nir_intrinsic_load_sbt_amd: + case nir_intrinsic_bvh64_intersect_ray_amd: type = RegType::vgpr; break; case nir_intrinsic_shuffle: diff --git a/src/amd/compiler/aco_opcodes.py b/src/amd/compiler/aco_opcodes.py index abe852caa36..a28f1d5d765 100644 --- a/src/amd/compiler/aco_opcodes.py +++ b/src/amd/compiler/aco_opcodes.py @@ -1509,6 +1509,7 @@ IMAGE_GATHER4 = { for (code, name) in IMAGE_GATHER4: opcode(name, code, code, code, Format.MIMG, InstrClass.VMem) +opcode("image_bvh64_intersect_ray", -1, -1, 231, Format.MIMG, InstrClass.VMem) FLAT = { #GFX7, GFX8_9, GFX10 _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
