Module: Mesa Branch: main Commit: f0f713960b17328712c84dde539a76b22a8bf38b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0f713960b17328712c84dde539a76b22a8bf38b
Author: Jason Ekstrand <[email protected]> Date: Fri Jun 18 09:17:01 2021 -0500 nir,amd: Suffix nir_op_cube_face_coord/index with _amd Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463> --- src/amd/compiler/aco_instruction_selection.cpp | 4 ++-- src/amd/compiler/aco_instruction_selection_setup.cpp | 4 ++-- src/amd/llvm/ac_nir_to_llvm.c | 8 ++++---- src/compiler/nir/nir_lower_alu_to_scalar.c | 4 ++-- src/compiler/nir/nir_opcodes.py | 4 ++-- src/compiler/spirv/vtn_amd.c | 4 ++-- src/gallium/auxiliary/gallivm/lp_bld_nir.c | 4 ++-- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 8f8b5348a0d..78d2137fff6 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2031,7 +2031,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } break; } - case nir_op_cube_face_coord: { + case nir_op_cube_face_coord_amd: { Temp in = get_alu_src(ctx, instr->src[0], 3); Temp src[3] = { emit_extract_vector(ctx, in, 0, v1), emit_extract_vector(ctx, in, 1, v1), @@ -2049,7 +2049,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc); break; } - case nir_op_cube_face_index: { + case nir_op_cube_face_index_amd: { Temp in = get_alu_src(ctx, instr->src[0], 3); Temp src[3] = { emit_extract_vector(ctx, in, 0, v1), emit_extract_vector(ctx, in, 1, v1), diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index c0f7b489b45..ef4d873446b 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -704,8 +704,8 @@ void init_context(isel_context *ctx, nir_shader *shader) case nir_op_ldexp: case nir_op_frexp_sig: case nir_op_frexp_exp: - case nir_op_cube_face_index: - case nir_op_cube_face_coord: + case nir_op_cube_face_index_amd: + case nir_op_cube_face_coord_amd: case nir_op_sad_u8x4: type = RegType::vgpr; break; diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 43950b31f98..0f611e2dfd2 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -578,8 +578,8 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) case nir_op_unpack_half_2x16: src_components = 1; break; - case nir_op_cube_face_coord: - case nir_op_cube_face_index: + case nir_op_cube_face_coord_amd: + case nir_op_cube_face_index_amd: src_components = 3; break; case nir_op_pack_64_4x16: @@ -1180,7 +1180,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) break; } - case nir_op_cube_face_coord: { + case nir_op_cube_face_coord_amd: { src[0] = ac_to_float(&ctx->ac, src[0]); LLVMValueRef results[2]; LLVMValueRef in[3]; @@ -1201,7 +1201,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) break; } - case nir_op_cube_face_index: { + case nir_op_cube_face_index_amd: { src[0] = ac_to_float(&ctx->ac, src[0]); LLVMValueRef in[3]; for (unsigned chan = 0; chan < 3; chan++) diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src/compiler/nir/nir_lower_alu_to_scalar.c index e72f17f99c7..023cecefca0 100644 --- a/src/compiler/nir/nir_lower_alu_to_scalar.c +++ b/src/compiler/nir/nir_lower_alu_to_scalar.c @@ -125,8 +125,8 @@ lower_alu_instr_scalar(nir_builder *b, nir_instr *instr, void *_data) case nir_op_vec4: case nir_op_vec3: case nir_op_vec2: - case nir_op_cube_face_coord: - case nir_op_cube_face_index: + case nir_op_cube_face_coord_amd: + case nir_op_cube_face_index_amd: /* We don't need to scalarize these ops, they're the ones generated to * group up outputs into a value that can be SSAed. */ diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index b39c7b57498..a692c4ecc9c 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -514,7 +514,7 @@ for (unsigned bit = 0; bit < bit_size; bit++) { """) # AMD_gcn_shader extended instructions -unop_horiz("cube_face_coord", 2, tfloat32, 3, tfloat32, """ +unop_horiz("cube_face_coord_amd", 2, tfloat32, 3, tfloat32, """ dst.x = dst.y = 0.0; float absX = fabsf(src0.x); float absY = fabsf(src0.y); @@ -536,7 +536,7 @@ dst.x = dst.x * (1.0f / ma) + 0.5f; dst.y = dst.y * (1.0f / ma) + 0.5f; """) -unop_horiz("cube_face_index", 1, tfloat32, 3, tfloat32, """ +unop_horiz("cube_face_index_amd", 1, tfloat32, 3, tfloat32, """ float absX = fabsf(src0.x); float absY = fabsf(src0.y); float absZ = fabsf(src0.z); diff --git a/src/compiler/spirv/vtn_amd.c b/src/compiler/spirv/vtn_amd.c index 623ff1205d7..85df179d91c 100644 --- a/src/compiler/spirv/vtn_amd.c +++ b/src/compiler/spirv/vtn_amd.c @@ -33,10 +33,10 @@ vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, SpvOp ext_opcode, nir_ssa_def *def; switch ((enum GcnShaderAMD)ext_opcode) { case CubeFaceIndexAMD: - def = nir_cube_face_index(&b->nb, vtn_get_nir_ssa(b, w[5])); + def = nir_cube_face_index_amd(&b->nb, vtn_get_nir_ssa(b, w[5])); break; case CubeFaceCoordAMD: - def = nir_cube_face_coord(&b->nb, vtn_get_nir_ssa(b, w[5])); + def = nir_cube_face_coord_amd(&b->nb, vtn_get_nir_ssa(b, w[5])); break; case TimeAMD: { def = nir_pack_64_2x32(&b->nb, nir_shader_clock(&b->nb, NIR_SCOPE_SUBGROUP)); diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c index f144f39b083..d932c9f11f7 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c @@ -997,8 +997,8 @@ static void visit_alu(struct lp_build_nir_context *bld_base, const nir_alu_instr case nir_op_unpack_half_2x16: src_components = 1; break; - case nir_op_cube_face_coord: - case nir_op_cube_face_index: + case nir_op_cube_face_coord_amd: + case nir_op_cube_face_index_amd: src_components = 3; break; case nir_op_fsum2: _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
