Module: Mesa Branch: main Commit: 3d1ca01e4140b87d7350e8b85d9e907d337d5674 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d1ca01e4140b87d7350e8b85d9e907d337d5674
Author: Marek Olšák <[email protected]> Date: Fri Sep 10 15:03:27 2021 -0400 radeonsi: fix DCC image stores with display DCC Fixes: 34a2c753107 - radeonsi: enable DCC stores on gfx10.3 APUs for better performance Tested-by: Joshua Ashton <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12809> --- src/gallium/drivers/radeonsi/si_descriptors.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index c9fea8cf002..93c9f28bee7 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -360,9 +360,19 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) | S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8) | - /* DCC image stores require INDEPENDENT_128B_BLOCKS, which is not set - * with displayable DCC on Navi12-14 due to DCN limitations. */ - S_00A018_WRITE_COMPRESS_ENABLE(tex->surface.u.gfx9.color.dcc.independent_128B_blocks && + /* DCC image stores require the following settings: + * - INDEPENDENT_64B_BLOCKS = 0 + * - INDEPENDENT_128B_BLOCKS = 1 + * - MAX_COMPRESSED_BLOCK_SIZE = 128B + * - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used) + * + * The same limitations apply to SDMA compressed stores because + * SDMA uses the same DCC codec. + */ + S_00A018_WRITE_COMPRESS_ENABLE(!tex->surface.u.gfx9.color.dcc.independent_64B_blocks && + tex->surface.u.gfx9.color.dcc.independent_128B_blocks && + tex->surface.u.gfx9.color.dcc.max_compressed_block_size == + V_028C78_MAX_BLOCK_SIZE_128B && access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE); }
