Module: Mesa Branch: main Commit: 68d4d09b569fb0ab179b9706d33a0e64108b0a22 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=68d4d09b569fb0ab179b9706d33a0e64108b0a22
Author: Rob Clark <[email protected]> Date: Tue Sep 14 11:29:00 2021 -0700 freedreno: Add info->a6xx.has_shading_rate @flto noticed these registers seem to be related to GL_QCOM_shading_rate Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856> --- src/freedreno/common/freedreno_dev_info.h | 3 +++ src/freedreno/common/freedreno_devices.py | 1 + src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c | 9 +-------- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index a5b6f7cef4e..5171acc9b76 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -69,6 +69,9 @@ struct fd_dev_info { bool tess_use_shared; + /* Does the hw support GL_QCOM_shading_rate? */ + bool has_shading_rate; + /* newer a6xx allows using 16-bit descriptor for both 16-bit * and 32-bit access */ diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index 3454c053f99..b76c874883e 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -243,6 +243,7 @@ a6xx_gen4 = dict( has_cp_reg_write = False, has_8bpp_ubwc = False, has_lpac = True, + has_shading_rate = True, ) add_gpus([ diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c index 367560a9536..7ef8a309688 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c @@ -94,14 +94,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, OUT_REG(ring, A6XX_VPC_POLYGON_MODE(mode)); OUT_REG(ring, A6XX_PC_POLYGON_MODE(mode)); - /* These started showing up in a6xx gen3, but so far I haven't found - * any example of blob setting them to anything other than zero. - * - * Probably not related to tess_use_shared, but that is a convenient - * thing to key off of until we find whatever new feature gen3 added - * that uses these registers. - */ - if (ctx->screen->info->a6xx.tess_use_shared) { + if (ctx->screen->info->a6xx.has_shading_rate) { OUT_REG(ring, A6XX_RB_UNKNOWN_8A00()); OUT_REG(ring, A6XX_RB_UNKNOWN_8A10()); OUT_REG(ring, A6XX_RB_UNKNOWN_8A20());
