Module: Mesa Branch: main Commit: d7b0ddbfa89017608767df2e70dd8a8bfeb78b48 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7b0ddbfa89017608767df2e70dd8a8bfeb78b48
Author: Marek Olšák <[email protected]> Date: Sun Sep 26 02:20:52 2021 -0400 radeonsi: use the optimal draw packet sequence for VGT_FLUSH Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13048> --- src/gallium/drivers/radeonsi/si_state_draw.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 78ddd564e53..73eaa2d86ae 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -2267,7 +2267,7 @@ static void si_draw_vbo(struct pipe_context *ctx, /* Use optimal packet order based on whether we need to sync the pipeline. */ if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH | - SI_CONTEXT_VS_PARTIAL_FLUSH))) { + SI_CONTEXT_VS_PARTIAL_FLUSH | SI_CONTEXT_VGT_FLUSH))) { /* If we have to wait for idle, set all states first, so that all * SET packets are processed in parallel with previous draw calls. * Then draw and prefetch at the end. This ensures that the time
