Module: Mesa Branch: main Commit: 40a93e271cf4414a29a365e03b16c133f3765816 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40a93e271cf4414a29a365e03b16c133f3765816
Author: Daniel Schürmann <[email protected]> Date: Tue Sep 28 17:11:28 2021 +0100 aco: clang-format No changes, just formatting. Reviewed-by: Timur Kristóf <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13087> --- src/amd/compiler/aco_instruction_selection.cpp | 6 ++++-- src/amd/compiler/aco_instruction_selection_setup.cpp | 9 +++------ src/amd/compiler/aco_live_var_analysis.cpp | 3 +-- src/amd/compiler/aco_lower_to_cssa.cpp | 3 ++- src/amd/compiler/aco_optimizer.cpp | 7 +++---- src/amd/compiler/aco_optimizer_postRA.cpp | 7 ++++--- src/amd/compiler/aco_register_allocation.cpp | 2 +- 7 files changed, 18 insertions(+), 19 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 89b4dc7b170..9953130630c 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -8971,11 +8971,13 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) Temp gs_invocation_id = get_arg(ctx, ctx->args->ac.gs_invocation_id); /* Get initial edgeflags for each vertex at bits 8, 9, 10 of gs_invocation_id. */ - Temp flags = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand::c32(0x700u), gs_invocation_id); + Temp flags = + bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand::c32(0x700u), gs_invocation_id); /* Move the bits to their desired position: 8->9, 9->19, 10->29. */ flags = bld.vop2(aco_opcode::v_mul_u32_u24, bld.def(v1), Operand::c32(0x80402u), flags); /* Remove garbage bits that are a byproduct of the multiplication. */ - bld.vop2(aco_opcode::v_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand::c32(0x20080200), flags); + bld.vop2(aco_opcode::v_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), + Operand::c32(0x20080200), flags); break; } case nir_intrinsic_load_packed_passthrough_primitive_amd: { diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 8b7fe4f5395..166ba5af819 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -339,8 +339,7 @@ setup_vs_variables(isel_context* ctx, nir_shader* nir) { if (ctx->stage == vertex_vs || ctx->stage == vertex_ngg) { radv_vs_output_info* outinfo = &ctx->program->info->vs.outinfo; - setup_vs_output_info(ctx, nir, outinfo->export_prim_id, - outinfo->export_clip_dists, outinfo); + setup_vs_output_info(ctx, nir, outinfo->export_prim_id, outinfo->export_clip_dists, outinfo); /* TODO: NGG streamout */ if (ctx->stage.hw == HWStage::NGG) @@ -363,8 +362,7 @@ setup_gs_variables(isel_context* ctx, nir_shader* nir) ctx->program->info->gs_ring_info.lds_size; /* Already in units of the alloc granularity */ } else if (ctx->stage == vertex_geometry_ngg || ctx->stage == tess_eval_geometry_ngg) { radv_vs_output_info* outinfo = &ctx->program->info->vs.outinfo; - setup_vs_output_info(ctx, nir, false, outinfo->export_clip_dists, - outinfo); + setup_vs_output_info(ctx, nir, false, outinfo->export_clip_dists, outinfo); ctx->program->config->lds_size = DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule); @@ -392,8 +390,7 @@ setup_tes_variables(isel_context* ctx, nir_shader* nir) if (ctx->stage == tess_eval_vs || ctx->stage == tess_eval_ngg) { radv_vs_output_info* outinfo = &ctx->program->info->tes.outinfo; - setup_vs_output_info(ctx, nir, outinfo->export_prim_id, - outinfo->export_clip_dists, outinfo); + setup_vs_output_info(ctx, nir, outinfo->export_prim_id, outinfo->export_clip_dists, outinfo); /* TODO: NGG streamout */ if (ctx->stage.hw == HWStage::NGG) diff --git a/src/amd/compiler/aco_live_var_analysis.cpp b/src/amd/compiler/aco_live_var_analysis.cpp index bd3522e915d..48456fc0df8 100644 --- a/src/amd/compiler/aco_live_var_analysis.cpp +++ b/src/amd/compiler/aco_live_var_analysis.cpp @@ -388,8 +388,7 @@ update_vgpr_sgpr_demand(Program* program, const RegisterDemand new_demand) */ unsigned lds_bytes_per_interp = 3 * 16; unsigned lds_param_bytes = lds_bytes_per_interp * program->info->ps.num_interp; - lds_per_workgroup += - align(lds_param_bytes, program->dev.lds_alloc_granule); + lds_per_workgroup += align(lds_param_bytes, program->dev.lds_alloc_granule); } if (lds_per_workgroup) diff --git a/src/amd/compiler/aco_lower_to_cssa.cpp b/src/amd/compiler/aco_lower_to_cssa.cpp index cbd9873c32b..753a869cc41 100644 --- a/src/amd/compiler/aco_lower_to_cssa.cpp +++ b/src/amd/compiler/aco_lower_to_cssa.cpp @@ -486,7 +486,8 @@ emit_parallelcopies(cssa_ctx& ctx) /* emit VGPR copies */ auto IsLogicalEnd = [](const aco_ptr<Instruction>& inst) -> bool { return inst->opcode == aco_opcode::p_logical_end; }; - auto it = std::find_if(block.instructions.rbegin(), block.instructions.rend(), IsLogicalEnd); + auto it = + std::find_if(block.instructions.rbegin(), block.instructions.rend(), IsLogicalEnd); bld.reset(&block.instructions, std::prev(it.base())); emit_copies_block(bld, ltg, RegType::vgpr); } diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index 5f528179fd9..6773b96eacc 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -2512,8 +2512,7 @@ combine_add_bcnt(opt_ctx& ctx, aco_ptr<Instruction>& instr) for (unsigned i = 0; i < 2; i++) { Instruction* op_instr = follow_operand(ctx, instr->operands[i]); if (op_instr && op_instr->opcode == aco_opcode::v_bcnt_u32_b32 && - !op_instr->usesModifiers() && - op_instr->operands[0].isTemp() && + !op_instr->usesModifiers() && op_instr->operands[0].isTemp() && op_instr->operands[0].getTemp().type() == RegType::vgpr && op_instr->operands[1].constantEquals(0)) { aco_ptr<Instruction> new_instr{ @@ -3517,8 +3516,8 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) } } else if (instr->opcode == aco_opcode::v_sub_u32 || instr->opcode == aco_opcode::v_sub_co_u32 || instr->opcode == aco_opcode::v_sub_co_u32_e64) { - bool carry_out = instr->opcode != aco_opcode::v_sub_u32 && - ctx.uses[instr->definitions[1].tempId()] > 0; + bool carry_out = + instr->opcode != aco_opcode::v_sub_u32 && ctx.uses[instr->definitions[1].tempId()] > 0; if (combine_add_sub_b2i(ctx, instr, aco_opcode::v_subbrev_co_u32, 2)) { } else if (!carry_out && combine_add_lshl(ctx, instr, true)) { } diff --git a/src/amd/compiler/aco_optimizer_postRA.cpp b/src/amd/compiler/aco_optimizer_postRA.cpp index c24c0fadd72..0d9eee82870 100644 --- a/src/amd/compiler/aco_optimizer_postRA.cpp +++ b/src/amd/compiler/aco_optimizer_postRA.cpp @@ -125,9 +125,10 @@ last_writer_idx(pr_opt_ctx& ctx, PhysReg physReg, RegClass rc) Idx instr_idx = ctx.instr_idx_by_regs[ctx.current_block->index][physReg.reg()]; unsigned dw_size = DIV_ROUND_UP(rc.bytes(), 4u); unsigned r = physReg.reg(); - bool all_same = std::all_of(ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r, - ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r + dw_size, - [instr_idx](Idx i) { return i == instr_idx; }); + bool all_same = + std::all_of(ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r, + ctx.instr_idx_by_regs[ctx.current_block->index].begin() + r + dw_size, + [instr_idx](Idx i) { return i == instr_idx; }); return all_same ? instr_idx : written_by_multiple_instrs; } diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index e788aeb4410..9766dfc3151 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -1224,7 +1224,7 @@ get_reg_impl(ra_ctx& ctx, RegisterFile& reg_file, } /* we cannot split live ranges of linear vgprs inside control flow */ - //TODO: ensure that live range splits inside control flow are never necessary + // TODO: ensure that live range splits inside control flow are never necessary if (!(ctx.block->kind & block_kind_top_level) && ctx.assignments[reg_file[j]].rc.is_linear_vgpr()) { found = false;
