Module: Mesa Branch: main Commit: 1048e6113ea288d8bc3849d8b44c4d002518d46f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1048e6113ea288d8bc3849d8b44c4d002518d46f
Author: Emma Anholt <[email protected]> Date: Sun Dec 26 09:07:32 2021 -0800 nir_to_tgsi: Use nir_opt_offsets for load_ubo_vec4. This helps non-native-integers hardware where relative addressing of UBOs has a constant offset field, and having addressing math (particularly for D3D9) emitted as ALU ops ends up running us out of constants. For native-integers drivers (such as softpipe), the possible-overflow check typically triggers and we end up not folding. r300: total instructions in shared programs: 1279167 -> 1278731 (-0.03%) instructions in affected programs: 50834 -> 50398 (-0.86%) total temps in shared programs: 213736 -> 213687 (-0.02%) temps in affected programs: 598 -> 549 (-8.19%) total consts in shared programs: 952973 -> 952850 (-0.01%) consts in affected programs: 26776 -> 26653 (-0.46%) Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14309> --- src/gallium/auxiliary/nir/nir_to_tgsi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index df76d50af51..ce679418e99 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -2573,6 +2573,21 @@ ntt_optimize_nir(struct nir_shader *s, struct pipe_screen *screen) NIR_PASS(progress, s, nir_opt_undef); NIR_PASS(progress, s, nir_opt_loop_unroll); + /* Try to fold addressing math into ubo_vec4's base to avoid load_consts + * and ALU ops for it. + */ + static const nir_opt_offsets_options offset_options = { + .ubo_vec4_max = ~0, + + /* No const offset in TGSI for shared accesses. */ + .shared_max = 0, + + /* unused intrinsics */ + .uniform_max = 0, + .buffer_max = 0, + }; + NIR_PASS(progress, s, nir_opt_offsets, &offset_options); + } while (progress); }
