Module: Mesa Branch: main Commit: 945fb51fb59d52223b5c0fe90c37d1cba42eb53c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=945fb51fb59d52223b5c0fe90c37d1cba42eb53c
Author: Ian Romanick <[email protected]> Date: Tue Jan 18 16:30:37 2022 -0800 intel/fs: Fix gl_FrontFacing optimization on Gfx12+ It's not obvious why the (gl_FrontFacing ? -1.0 : 1.0) case was handled different for Gfx12+ than for previous generations, and it's not correct. It tries to negate the result as an integer, and it does this before the mask operation that clears the other bits in the value. When we eventually support dual-SIMD8 dispatch, the other front-facing bit is in g1.6 at bit 15, so similar code should be possible there. Reviewed-by: Matt Turner <[email protected]> Fixes: c92fb60007f ("intel/fs/gen12: Implement gl_FrontFacing on gen12+.") Closes: #5876 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14625> --- src/intel/compiler/brw_fs_nir.cpp | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 1a15c0d9561..f1a635c4fd4 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -562,17 +562,16 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr, /* For (gl_FrontFacing ? 1.0 : -1.0), emit: * - * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W + * or(8) tmp.1<2>W g1.1<0,1,0>W 0x00003f80W * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D * - * and negate the result for (gl_FrontFacing ? -1.0 : 1.0). + * and negate g1.1<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0). */ - bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), - g1, brw_imm_uw(0x3f80)); - if (value1 == -1.0f) - bld.MOV(tmp, negate(tmp)); + g1.negate = true; + bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), + g1, brw_imm_uw(0x3f80)); } else if (devinfo->ver >= 6) { /* Bit 15 of g0.0 is 0 if the polygon is front facing. */ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
