URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=343b57c070ff6610ae1ff58f495e640bae6f598c
Author: Lionel Landwerlin <[email protected]>
Date: Mon Jan 31 12:43:04 2022 +0000
anv/genxml/intel/fs: fix binding shader record entry
Bit is flipped compared to all the other packets.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: 705395344d25 ("intel/fs: Add support for compiling bindless shaders
with resume shaders")
Fixes: c3ac9afca389 ("anv: Create and return ray-tracing pipeline SBT
handles")
Acked-by: Jason Ekstrand <[email protected]>
Reviewed-by: Caio Oliveira <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15078>
(cherry picked from commit 2763a8af5ac3739c677ed7de7bd2a7e60a35f822)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3867d0737608654915b6008609cdb51448a2eaef
Author: Alyssa Rosenzweig <[email protected]>
Date: Fri Jul 23 16:49:02 2021 -0400
pan/bi: Lower swizzles on CSEL.i32/MUX.i32
This is counter-intuitive, but required for correct operation when
CSEL.i32 takes a 1-bit (stored 16-bit) boolean argument. The impedance
mismatch ultimately is between CSEL.b32 (nir's bcsel, nonexistant in the
hardware) and the lowering CSEL.i32. However, a similar problem exists
even with MUX.i32 which lacks a good way of zero/sign-extending
booleans.
Cherry-picked from my Valhall branch though the issue also affects
Bifrost. Fixes piglit shaders@glsl-vs-if-bool on Bifrost.
Unfortunately, shader-db is quite unhappy :-(
The proper fix is to use lower_bool_to_bitsize, but that can't be
backported to mesa-stable.
total instructions in shared programs: 157539 -> 158953 (0.90%)
instructions in affected programs: 55621 -> 57035 (2.54%)
helped: 2
HURT: 259
helped stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 2.11% max: 2.67% x̄: 2.39% x̃: 2.39%
HURT stats (abs) min: 1.0 max: 40.0 x̄: 5.47 x̃: 2
HURT stats (rel) min: 0.36% max: 16.13% x̄: 2.55% x̃: 1.59%
95% mean confidence interval for instructions value: 4.44 6.40
95% mean confidence interval for instructions %-change: 2.21% 2.82%
Instructions are HURT.
total tuples in shared programs: 132322 -> 132907 (0.44%)
tuples in affected programs: 31806 -> 32391 (1.84%)
helped: 5
HURT: 152
helped stats (abs) min: 1.0 max: 2.0 x̄: 1.40 x̃: 1
helped stats (rel) min: 0.39% max: 3.03% x̄: 1.70% x̃: 1.61%
HURT stats (abs) min: 1.0 max: 42.0 x̄: 3.89 x̃: 2
HURT stats (rel) min: 0.29% max: 18.18% x̄: 2.50% x̃: 1.79%
95% mean confidence interval for tuples value: 2.88 4.58
95% mean confidence interval for tuples %-change: 1.87% 2.85%
Tuples are HURT.
total clauses in shared programs: 28672 -> 28698 (0.09%)
clauses in affected programs: 869 -> 895 (2.99%)
helped: 1
HURT: 24
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 5.88% max: 5.88% x̄: 5.88% x̃: 5.88%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.12 x̃: 1
HURT stats (rel) min: 0.49% max: 33.33% x̄: 8.46% x̃: 3.59%
95% mean confidence interval for clauses value: 0.82 1.26
95% mean confidence interval for clauses %-change: 3.84% 11.93%
Clauses are HURT.
total cycles in shared programs: 15119.04 -> 15137.88 (0.12%)
cycles in affected programs: 922.87 -> 941.71 (2.04%)
helped: 4
HURT: 79
helped stats (abs) min: 0.0416669999999999 max: 0.0833330000000001 x̄: 0.05
x̃: 0
helped stats (rel) min: 0.40% max: 3.17% x̄: 1.57% x̃: 1.35%
HURT stats (abs) min: 0.041665999999999315 max: 1.75 x̄: 0.24 x̃: 0
HURT stats (rel) min: 0.30% max: 20.00% x̄: 2.83% x̃: 2.12%
95% mean confidence interval for cycles value: 0.17 0.29
95% mean confidence interval for cycles %-change: 1.86% 3.37%
Cycles are HURT.
total arith in shared programs: 4922.71 -> 4947.71 (0.51%)
arith in affected programs: 1423.79 -> 1448.79 (1.76%)
helped: 5
HURT: 177
helped stats (abs) min: 0.0416669999999999 max: 0.0833330000000001 x̄: 0.06
x̃: 0
helped stats (rel) min: 0.40% max: 3.17% x̄: 1.82% x̃: 1.67%
HURT stats (abs) min: 0.041665999999999315 max: 1.75 x̄: 0.14 x̃: 0
HURT stats (rel) min: 0.30% max: 22.22% x̄: 2.50% x̃: 1.52%
95% mean confidence interval for arith value: 0.11 0.17
95% mean confidence interval for arith %-change: 1.86% 2.90%
Arith are HURT.
total quadwords in shared programs: 120605 -> 120956 (0.29%)
quadwords in affected programs: 26535 -> 26886 (1.32%)
helped: 6
HURT: 143
helped stats (abs) min: 1.0 max: 7.0 x̄: 2.83 x̃: 1
helped stats (rel) min: 0.93% max: 6.33% x̄: 2.29% x̃: 1.71%
HURT stats (abs) min: 1.0 max: 21.0 x̄: 2.57 x̃: 2
HURT stats (rel) min: 0.34% max: 13.79% x̄: 2.02% x̃: 1.22%
95% mean confidence interval for quadwords value: 1.86 2.86
95% mean confidence interval for quadwords %-change: 1.45% 2.24%
Quadwords are HURT.
total threads in shared programs: 4670 -> 4669 (-0.02%)
threads in affected programs: 2 -> 1 (-50.00%)
helped: 0
HURT: 1
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14576>
(cherry picked from commit 8bd4976d981a9a98ce7e419b25c05d38ccac027b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=481202353d5c606d1eb680646ba2ead3e339b060
Author: Alyssa Rosenzweig <[email protected]>
Date: Thu Feb 17 19:34:04 2022 -0500
pan/bi: Avoid *FADD.v2f16 hazard in scheduler
Obscure encoding restriction. Fixes crash (assertion fail when instruction
packing) in asphalt9/2659.shader_test on Bifrost.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072>
(cherry picked from commit 24d2bdb1e050134a25924487792ee0018f8478ae)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a83c6f54de6e54b4f08876239d5f01deef69c7d8
Author: Alyssa Rosenzweig <[email protected]>
Date: Thu Feb 17 19:33:29 2022 -0500
pan/bi: Avoid *FADD.v2f16 hazard in optimizer
This is a very obscure encoding restriction in the Bifrost ISA. Unknown if
any
real apps or tests hit this, but we still need to get it right sadly.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072>
(cherry picked from commit 8e0eb592d5bbcf00f8bed55cc95013abf77fad12)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94184ce3f802de69440e3834dd13f27e008ab3ca
Author: Ian Romanick <[email protected]>
Date: Wed Feb 16 14:02:16 2022 -0800
nir: Add missing dependency on nir_opcodes.py
Commit 38800b38 changed nir_opcodes.py, but that doesn't seem to have
triggered nir_opt_algebraic.py. The change in 75ef5991 depends on
opt_algebraic lowering 16-bit versions of slt, but if opt_algebraic is
not rebuilt, this may not happen. This resulted in some people seeing
assertion failures in, for example,
dEQP-VK.spirv_assembly.instruction.compute.float16.arithmetic_3.step,
due to the backend seeing nir_op_slt that it didn't know how to handle.
v2: Add nir_opcodes.py to nir_algebraic_py so that all the per-driver
algebraic passes pick up the dependency too. Rename it to
nir_algebraic_depends. Suggested by Emma.
Closes: #6047
Fixes: d1992255bb2 ("meson: Add build Intel "anv" vulkan driver")
Reviewed-by: Emma Anholt <[email protected]>
Acked-by: Dave Airlie <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15050>
(cherry picked from commit a01b26299039496ca7ed04878cbb64a18af3037c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a464c48743db9f559f602d3e087669b3a01ac73
Author: Lionel Landwerlin <[email protected]>
Date: Wed Feb 16 23:14:15 2022 +0200
nir: fix lower_memcpy
memcpy is divided into chunks that are vec4 sized max. The problem
here happens with a structure of 24 bytes :
struct {
float3 a;
float3 b;
}
If you memcpy that struct, the lowering will emit 2 load/store, one of
sized 8, next one sized 16. But both end up located at offset 0, so we
effectively drop 2 floats.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: a3177cca996145 ("nir: Add a lowering pass to lower memcpy")
Reviewed-by: Jason Ekstrand <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15049>
(cherry picked from commit 768930a73a43e48172df00b6c934de582bd9422b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e44f3f691dfd805b0ab9b30f7e4fb786a64bf2a
Author: Dave Airlie <[email protected]>
Date: Tue Feb 8 16:33:38 2022 +1000
lavapipe: reference gallium fences correctly.
Make sure to take references in all the correct places to get
right lifetimes for these objects and avoid leaks.
Fixes: 94a498280516 ("lavapipe: implement timeline semaphores")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15046>
(cherry picked from commit b805d3e6abc07c8a6865516707854d295791e862)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b49271cc60b8dc0ffbc91f2f5b5f5be9eac9a0f
Author: Thierry Reding <[email protected]>
Date: Wed Oct 6 22:47:17 2021 +0200
tegra: Use private reference count for resources
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on resources can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: 7688b8ae9802 ("st/mesa: eliminate all atomic ops when setting vertex
buffers")
Reviewed-by: Karol Herbst <[email protected]>
Tested-by: Karol Herbst <[email protected]>
(cherry picked from commit 108e6eaa83eed3eb356f3cce835c5f5e3a836b8e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d25c9f7b8c5bee965df0c57ef1305473208367c
Author: Thierry Reding <[email protected]>
Date: Wed Oct 6 22:42:36 2021 +0200
tegra: Use private reference count for sampler views
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on sampler views can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: ef5d42741327 ("st/mesa: add a mechanism to bypass atomics when
binding sampler views")
Reviewed-by: Karol Herbst <[email protected]>
Tested-by: Karol Herbst <[email protected]>
(cherry picked from commit e8ce0a335704af54b8269d6e862835703700392b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa4b404b25feda2b51baf1d23d127b93c253fc72
Author: Timur Kristóf <[email protected]>
Date: Sat Feb 12 17:27:41 2022 +0100
radv: Disable IB2 on compute queues.
The "IB2" indirect buffer command is not supported on compute queues
according to PAL, and it indeed causes GPU hangs when task shaders are
used together with vkCmdExecuteCommands.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15006>
(cherry picked from commit da719792ad2b7f50824fd1ba500f8b87e4b3b448)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d983739ba1c1d4838df3e9afa481f698323e7901
Author: Connor Abbott <[email protected]>
Date: Wed Nov 24 17:51:19 2021 +0100
ir3/spill: Fix simplify_phi_nodes with multiple loop nesting
Once we simplified a phi node, we never updated the definition it points
to, which meant that it could become out of date if that definition were
also simplified, and we didn't check that when rewriting sources. That
could happen when there are multiple nested loops with phi nodes at the
header.
Fix it by updating the phi's pointer. Since we always update sources
after visiting the definition it points to, when we go to rewrite a
source, if that source points to a simplified phi, the phi's pointer
can't be pointing to a simplified phi because we already visited the phi
earlier in the pass and updated it, or else it's been simplified in the
meantime and this isn't the last pass. This way we don't need to
keep recursing when rewriting sources.
Fixes: 613eaac7b53 ("ir3: Initial support for spilling non-shared
registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15035>
(cherry picked from commit 3ef858a6f6789207e3f24550e9dfb595e3018029)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fad9a9456fbbe891bbd701b16ac8a81559737ba7
Author: Tapani Pälli <[email protected]>
Date: Tue Feb 15 10:22:15 2022 +0200
mesa/st: always use DXT5 when transcoding ASTC format
This fixes artifacts seen in games when using ASTC transcoding,
we need to use DXT5 for proper alpha channel support.
Number of components is a block specific property, there is no easy
way to see if we will require >1bit alpha support or not, so simply
use DXT5 to have support in place.
Fixes: 91cbe8d855c ("gallium: Add a transcode_astc driconf option")
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15029>
(cherry picked from commit d3b4202b63cb3aca42bc91c5bc416acc1b7f382b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ff941fed51617fd304beb8e729bd62caf82130b
Author: Yiwei Zhang <[email protected]>
Date: Tue Feb 15 20:15:57 2022 +0000
venus: properly destroy deferred ahb image before real image creation
Fixes: 19b7b09885c ("venus: prepare image creation helpers for AHB")
Signed-off-by: Yiwei Zhang <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15037>
(cherry picked from commit 9dd15295e30b3dd5a75440dab05a1eb4019ef1a8)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b534fc1a552e51042b31d3466a2566782296f7df
Author: Emma Anholt <[email protected]>
Date: Sat Feb 5 20:11:25 2022 -0800
i915g: Initialize the rest of the "from_nir" temporary VS struct.
draw looked at the uninitialized XFB state, which should just be zeroed
out since i915 doesn't have XFB.
Fixes: 2b3fc26da8be ("i915g: Switch to using nir-to-tgsi.")
Reviewed-by: Zoltán Böszörményi <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14896>
(cherry picked from commit 780949c62bc2cd1805f99911a76fde016e430b6b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62e6ce1b74af0c893bb4b82bda12231f00de582c
Author: Tapani Pälli <[email protected]>
Date: Mon Feb 14 07:40:51 2022 +0200
iris: fix a leak on surface states
Cc: mesa-stable
Closes:https://gitlab.freedesktop.org/mesa/mesa/-/issues/6013
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15010>
(cherry picked from commit ecc00410302cae4e22ad7718a531f03658190389)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22605af3841307e57885f7cc27409ac9399b25e2
Author: Mike Blumenkrantz <[email protected]>
Date: Thu Feb 10 14:30:25 2022 -0500
zink: always invalidate streamout counter buffer if not resuming
this otherwise treates begin/end/begin the same as begin/pause/resume
cc: mesa-stable
fixes:
KHR-GL46.texture_view.view_classes
KHR-GL46.transform_feedback.capture_geometry_separate_test
KHR-GL46.transform_feedback.capture_vertex_separate_test
KHR-GL46.transform_feedback.query_geometry_separate_test
KHR-GL46.transform_feedback.query_vertex_separate_test
Reviewed-by: Dave Airlie <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15020>
(cherry picked from commit e8ba9cee270417af29f2399ada05c2d104f1dc58)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5f20c7be0c157b3d4e77f43d55485aa3a0bd854
Author: Bas Nieuwenhuizen <[email protected]>
Date: Sat Jan 15 14:43:15 2022 +0100
radv: Fix preamble argument order.
Used the wrong cmdbuffer in the wrong situation. Oops.
Fixes: 915e9178faf ("radv: Split out commandbuffer submission.")
Reviewed-By: Tatsuyuki Ishi <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14574>
(cherry picked from commit 79131b6ee6c98a8b662aeb32bb623a8974f8bef5)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b3311039a602ced1e7d746474ef8e46d4f97330
Author: Samuel Pitoiset <[email protected]>
Date: Fri Feb 11 11:17:49 2022 +0100
radv/winsys: fix initializing debug/perftest options if multiple instances
Since the winsys uses refcount, options like RADV_DEBUG_ZERO_VRAM might
have not been initialized if the first instance wasn't created with
application info.
This fixes missing zerovram for vkd3d-proton.
Cc: 21.3 22.0 mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14978>
(cherry picked from commit aa3405e8123324b3d8173c709e6573d86570d99a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75e50842651fa5ab8506a2772291ddaadabb2a50
Author: Eric Engestrom <[email protected]>
Date: Sun Feb 20 16:28:09 2022 +0000
.pick_status.json: Mark b07372312d7053f2ef5c858ceb1fbf9ade5e7c52 as
denominated
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8393768c260e6b5123fcd0fafe4a8c61e931b6cc
Author: Jason Ekstrand <[email protected]>
Date: Tue Feb 8 16:04:34 2022 -0600
anv: Call vk_command_buffer_finish if create fails
This wasn't much of a problem before because vk_command_buffer_finish()
doesn't do much on an empty command buffer. However, it's about to be
responsible for managing the pool's list of command buffers so it will
be critical to get this right.
Fixes: c9189f481353 ("anv: Use a common vk_command_buffer structure")
Reviewed-by: Lionel Landwerlin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14917>
(cherry picked from commit 7b0e30685446d30aaea1c2c7c1fd04a658c74d94)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed63455d1a0659b5f4b380e8fed567455d98940b
Author: Mike Blumenkrantz <[email protected]>
Date: Wed Feb 9 16:13:29 2022 -0500
zink: always set VkPipelineMultisampleStateCreateInfo::pSampleMask
by initializing this on context creation, we can ensure that the correct
value is always here
cc: mesa-stable
fixes:
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_only
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_2.sample_mask_only
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_3.sample_mask_only
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_4.sample_mask_only
Reviewed-by: Dave Airlie <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14974>
(cherry picked from commit 8ff96efcfde15d5e8b83ce3b0b95a73254e98b69)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39da8ad437ae44f05df86dd030ab253dc22e9e06
Author: Ian Romanick <[email protected]>
Date: Fri Oct 29 10:50:55 2021 -0700
nir: Produce correct results for atan with NaN
Properly handling NaN adversely affects several hundred shaders in
shader-db (lots of Skia and a few others from various synthetic
benchmarks) and fossil-db (mostly Talos and some Doom 2016). Only apply
the NaN handling work-around when the shader demands it.
v2: Add comment explaining the 1.0*y_over_x. Suggested by Caio.
Reviewed-by: Caio Oliveira <[email protected]>
Fixes: 2098ae16c8b ("nir/builder: Move nir_atan and nir_atan2 from SPIR-V
translator")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 1cb3d1a6ae027b5045e47ccf7e551bd81fc3cab2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a77492cb0b9d2e8c300478b95f6cb4a0f18f040
Author: Ian Romanick <[email protected]>
Date: Thu Oct 28 17:34:56 2021 -0700
nir: Properly handle various exceptional values in frexp
frexp_sig of ±0, ±Inf, or NaN should just return the input unmodified.
frexp_exp of ±Inf or NaN is undefined, and frexp_exp of ±0 should return
the input unmodified. This seems to already work.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Oliveira <[email protected]>
Fixes: 23d30f4099f ("spirv,nir: lower frexp_exp/frexp_sig inside a new NIR
pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 7d0d9b9fbc231c2bd66778e0b0a62d5c514c5495)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f93d5e740164e4c427f77dc94b69bde3fda8d4c
Author: Ian Romanick <[email protected]>
Date: Fri Oct 29 10:51:25 2021 -0700
spirv: Produce correct result for GLSLstd450Tanh with NaN
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Oliveira <[email protected]>
Fixes: 9f9432d56c0 ("Revert "spirv: Use a simpler and more correct
implementaiton of tanh()"")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 93ed87af28e7f5b7db7bae095e5a37b63b7bd2c7)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d62727521789b21cae658f83b00c1ef1906ae287
Author: Ian Romanick <[email protected]>
Date: Fri Oct 29 08:15:18 2021 -0700
spirv: Produce correct result for GLSLstd450Modf with Inf
GLSLstd450ModfStruct too.
No shader-db or fossil-db changes on any Intel platform.
v2: Fix handling 16-bit (and presumably 64-bit) values.
Reviewed-by: Caio Oliveira <[email protected]>
Fixes: f92a35d831c ("vtn: Fix Modf.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit e442b9d79296ad9322af61fdadbc81d680466f57)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f7b2200337829b8bf09b7c8a163d07017b0e9da
Author: Ian Romanick <[email protected]>
Date: Thu Oct 28 17:33:02 2021 -0700
spriv: Produce correct result for GLSLstd450Step with NaN
NOTE: This commit needs "nir: All set-on-comparison opcodes can take all
float types" or regressions will occur in other Vulkan SPIR-V tests.
No shader-db changes on any Intel platform.
NOTE: This commit depends on "nir: All set-on-comparison opcodes can
take all float types".
v2: Fix handling 16-bit (and presumably 64-bit) values.
About 280 shaders in Talos are hurt by a few instructions, and a couple
shaders in Doom 2016 are hurt by a few instructions.
Tiger Lake
Instructions in all programs: 159893290 -> 159895026 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019260087 -> 7019254134 (-0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)
Ice Lake
Instructions in all programs: 143624235 -> 143625691 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440083238 -> 8440090702 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)
Skylake
Instructions in all programs: 134185495 -> 134186618 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366923 -> 8222365826 (-0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)
Reviewed-by: Caio Oliveira <[email protected]>
Fixes: 1feeee9cf47 ("nir/spirv: Add initial support for GLSL 4.50 builtins")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 75ef5991f5af06997551dabc053300261e32ca40)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a25ced69a3f6cf52fb00d8256ebf0a7e01fdd896
Author: Ian Romanick <[email protected]>
Date: Fri Oct 29 14:16:44 2021 -0700
intel/fs: Don't optimize out 1.0*x and -1.0*x
This (sort of) matches the behavior of nir_opt_algebraic. This ensures
that subnormal values are properly flushed to zero.
With the aid of "nir/search: Float sources of texture instructions are
float users" and "nir/search: Transitively apply is_only_used_as_float",
there would have been no shader-db regressions on Intel platforms.
However, those caused a significant increase in compile time. Since the
instruction regressions were so small, I just dropped those commits
rather than improve them.
All Haswell and newer platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20125042 -> 20125094 (<.01%)
instructions in affected programs: 7184 -> 7236 (0.72%)
helped: 0
HURT: 32
HURT stats (abs) min: 1 max: 4 x̄: 1.62 x̃: 2
HURT stats (rel) min: 0.11% max: 1.49% x̄: 0.85% x̃: 0.78%
95% mean confidence interval for instructions value: 1.39 1.86
95% mean confidence interval for instructions %-change: 0.74% 0.96%
Instructions are HURT.
total cycles in shared programs: 862745586 -> 862746551 (<.01%)
cycles in affected programs: 109872 -> 110837 (0.88%)
helped: 12
HURT: 23
helped stats (abs) min: 2 max: 774 x̄: 90.83 x̃: 19
helped stats (rel) min: 0.07% max: 25.23% x̄: 3.06% x̃: 0.40%
HURT stats (abs) min: 2 max: 1106 x̄: 89.35 x̃: 12
HURT stats (rel) min: 0.08% max: 45.40% x̄: 3.01% x̃: 0.47%
95% mean confidence interval for cycles value: -60.09 115.23
95% mean confidence interval for cycles %-change: -2.21% 4.07%
Inconclusive result (value mean confidence interval includes 0).
All of the shaders hurt are in either UE4 shooter-game or shooter_demo.
Tiger Lake
Instructions in all programs: 159893213 -> 159893290 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019259514 -> 7019260087 (+0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)
Ice Lake
Instructions in all programs: 143624164 -> 143624235 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440082767 -> 8440083238 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)
Skylake
Instructions in all programs: 134185424 -> 134185495 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366529 -> 8222366923 (+0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)
Reviewed-by: Caio Oliveira <[email protected]>
Fixes: f5dd6dfe012 ("anv: enable VK_KHR_shader_float_controls and
SPV_KHR_float_controls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 38a94c82e6ac3ae3e76e01ff4994ae4c46c487ec)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3faeb23bcc43aeaace95e6ef45ae0dd0364ce83e
Author: Ian Romanick <[email protected]>
Date: Tue Nov 30 09:45:49 2021 -0800
nir: All set-on-comparison opcodes can take all float types
Extend 4195a9450bde so that the next poor fool doesn't come along and
say, "sge does the right thing for 16-bit sources, but slt gives a NIR
validation failure. What the deuce?"
NOTE: This commit is necessary to prevent regressions in GLSLstd450Step
tests of 16-bit sources at "spriv: Produce correct result for
GLSLstd450Step with NaN".
Fixes: 4195a9450bd ("nir: sge operation is defined for floating-point
types")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 38800b385c6b4752ec1a91db5b8a7de149d03d0c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80716a6e2960e3e9ed557b3cec2f1302a54837de
Author: Nanley Chery <[email protected]>
Date: Mon Dec 27 10:15:19 2021 -0500
iris: Don't fast clear with the view format
Fast clear with the resource format instead. This is safe to do because
can_fast_clear_color ensures that the clear color generates the same
pixel with either the view format or the resource format.
On SKL, this prevents us from using an invalid surface state. This platform
doesn't support CCS_E with sRGB formats, but prior to this patch we allowed
fast-clearing with this combination. Piglit's fcc-write-after-clear test
can trigger this.
Fixes: 230952c2101 ("iris: Don't support sRGB + Y_TILED_CCS on gen9")
Reviewed-by: Kenneth Graunke <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>
(cherry picked from commit 6778b3a379d010d9b4d82e7324bff19d73cd3d1a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80e58899514eff6b521153840110456c1621ef2b
Author: Mike Blumenkrantz <[email protected]>
Date: Wed Feb 9 09:07:41 2022 -0500
aux/draw: fix llvm tcs lane vec generation
the idx param for LLVMBuildInsertElement is zero-indexed based on the
value of 'vector_length' (always 4), and the vector length is (obviously)
sized to 'vector_length', so this should be the member of the vec that is
being
inserted, not the invocation index
cc: mesa-stable
fixes (zink, but only on my one machine):
KHR-GL46.tessellation_shader.single.max_patch_vertices
KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
dEQP-GLES31.functional.tessellation.shader_input_output.barrier
dEQP-GLES31.functional.tessellation.shader_input_output.patch_vertices_5_in_10_out
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_point_mode_geometry_output_triangles
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_point_mode_geometry_output_lines
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_point_mode_geometry_output_lines
Reviewed-by: Dave Airlie <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14949>
(cherry picked from commit 68c1b50e48e32ec8ff4815666b7124d4cb4171ab)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6efe62a843220ce285bb6aeafe1311db949daf51
Author: Ian Romanick <[email protected]>
Date: Tue Feb 8 17:53:02 2022 -0800
gallivm/nir: Call nir_lower_bool_to_int32 after nir_opt_algebraic_late
All of the opcodes in nir_opt_algebraic_late are the unsized (1-bit)
versions. If the lowering to int32 happens first, many of the
optimizations and lowerings won't happen.
Of particular importance is the lowering of fisfinite. If a shader
happens to contain fisfinite of an fp16 value, it will assert later
during compliation.
Reviewed-by: Dave Airlie <[email protected]>
Fixes: 78b4e417d44 ("gallivm: handle fisfinite/fisnormal")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14942>
(cherry picked from commit e3cbc328e0dbb5865cc036ecbf977127850b4670)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f3f6f49e464f015ad867928751b26c2ffe804ce
Author: Qiang Yu <[email protected]>
Date: Wed Feb 9 09:40:22 2022 +0800
radeonsi: workaround Specviewperf13 Catia hang on GFX9
The root cause is unknown but PAL always update IA_MULTI_VGT_PARAM
whenever primitive type change.
cc: mesa-stable
Reviewed-by: Marek Olšák <[email protected]>
Singed-off-by: Qiang Yu <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14944>
(cherry picked from commit fe560aeb12516e766335d416ba749b7572637274)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0006e54fc56a1c871837f80eb70171d90687534a
Author: Tapani Pälli <[email protected]>
Date: Mon Jan 31 11:52:21 2022 +0200
iris: invalidate L3 read only cache when VF cache is invalidated
When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.
Ref: bspec 46314
Fixes: ed8f2c4cbee ("iris: Cache VB/IB in L3$ for Gen12")
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 562f7eef5b4f5a4d4fb4d93418e6373e853550fa)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=488652d8090432ef2e2a2bcb31f0c551221917a3
Author: Tapani Pälli <[email protected]>
Date: Mon Jan 31 11:49:53 2022 +0200
anv: invalidate L3 read only cache when VF cache is invalidated
When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.
Ref: bspec 46314
Fixes: 6c345ddbe40 ("anv: Cache VB/IB in L3$ for Gfx12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5941
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 7a6ea047954461d8f61878494265ba4bb84b50fe)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f950ce2dd9ba31f2537791580733bd7165d4286e
Author: Tapani Pälli <[email protected]>
Date: Mon Jan 31 11:48:49 2022 +0200
intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
Cc: mesa-stable
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 442628b70244f2c9fd0ed79e0656e999ee6fffca)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74758fa797b8bf1ca91df9a9f510a8788dc137ca
Author: Dave Airlie <[email protected]>
Date: Tue Feb 8 18:24:12 2022 +1000
lavapipe: fix sampler + sampler view leaks.
The compute sampler views are using a different method
of generation so have to be deleted explicitly.
Fixes: e94fd4cc6589 ("lavapipe: rename vallium to lavapipe")
Reviewed-By: Mike Blumenkrantz <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14939>
(cherry picked from commit 2f9089f6de8ca29a529ef7828efbabeec58be6e8)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fa3742f5db9f83012e084b5f567fa3992ec3a9d
Author: Pavel Ondračka <[email protected]>
Date: Mon Feb 7 16:49:38 2022 +0100
r300: fix transformation of abs modifiers with negate
It is being overwritten by the memset. Just set the only remaining
member RelAddr explicitly.
Signed-off-by: Pavel Ondračka <[email protected]>
Reviewed-by: Filip Gawin <[email protected]>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14915>
(cherry picked from commit 1f5330de3a6c54faf7a0ed7485c72a2ce40ac744)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3855f9221a2ff1e8c11081ed50ec7b1ee6c0f52c
Author: Mike Blumenkrantz <[email protected]>
Date: Mon Feb 7 12:37:32 2022 -0500
lavapipe: use util_pack_color_union() for generating clear colors
this enables clamping for packed formats (e.g., RGB10_A2UI) where color
values may exceed the width of the component
cc: mesa-stable
fixes (zink):
KHR-GL45.direct_state_access.renderbuffers_storage*
Reviewed-by: Dave Airlie <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14911>
(cherry picked from commit 08c2b9d7cbc2b60233c3d3ed411ceb9649fe5c9f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=483b9c3a585be58bb49eeb0aa6144671f1d179ca
Author: Eric Engestrom <[email protected]>
Date: Sun Feb 20 15:45:33 2022 +0000
.pick_status.json: Update to a814a4f9dba9ab660ab15be7a7cdf9f80e472d2b
