Module: Mesa Branch: staging/22.1 Commit: 0783dd7f7ef58f7a9afad909b344dcdc4518a92e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0783dd7f7ef58f7a9afad909b344dcdc4518a92e
Author: Samuel Pitoiset <[email protected]> Date: Tue Apr 26 14:20:56 2022 +0200 radv: allow to disable sinking of load inputs for FS via drirc To workaround game bugs where partial derivatives are used in non-uniform control flow. A proper solution needs to be implemented, but as a quick fix disabling nir_opt_sink() works. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16165> (cherry picked from commit 1dbfd2be4b13da08e097bfdcdb000283e4ebe741) --- .pick_status.json | 2 +- src/amd/vulkan/radv_device.c | 4 ++++ src/amd/vulkan/radv_pipeline.c | 14 ++++++++++++-- src/amd/vulkan/radv_private.h | 1 + src/amd/vulkan/radv_shader.h | 1 + src/util/driconf.h | 4 ++++ 6 files changed, 23 insertions(+), 3 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 3597210baaf..930ecdcc80b 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -139,7 +139,7 @@ "description": "radv: allow to disable sinking of load inputs for FS via drirc", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index b72e1091270..9f96242bd9b 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -959,6 +959,7 @@ static const driOptionDescription radv_dri_options[] = { DRI_CONF_RADV_REQUIRE_ETC2(false) DRI_CONF_RADV_DISABLE_HTILE_LAYERS(false) DRI_CONF_RADV_DISABLE_ANISO_SINGLE_LEVEL(false) + DRI_CONF_RADV_DISABLE_SINKING_LOAD_INPUT_FS(false) DRI_CONF_SECTION_END }; // clang-format on @@ -1010,6 +1011,9 @@ radv_init_dri_options(struct radv_instance *instance) instance->disable_aniso_single_level = driQueryOptionb(&instance->dri_options, "radv_disable_aniso_single_level"); + + instance->disable_sinking_load_input_fs = + driQueryOptionb(&instance->dri_options, "radv_disable_sinking_load_input_fs"); } VKAPI_ATTR VkResult VKAPI_CALL diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 3086ef24d19..a54f2930938 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3099,6 +3099,9 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline, key.use_ngg = pipeline->device->physical_device->use_ngg; key.adjust_frag_coord_z = pipeline->device->adjust_frag_coord_z; + if (pipeline->device->instance->disable_sinking_load_input_fs) + key.disable_sinking_load_input_fs = true; + return key; } @@ -4408,7 +4411,11 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout .allow_fp16 = device->physical_device->rad_info.chip_class >= GFX9, }); - nir_opt_sink(stages[i].nir, nir_move_load_input | nir_move_const_undef | nir_move_copies); + nir_move_options sink_opts = nir_move_const_undef | nir_move_copies; + if (i != MESA_SHADER_FRAGMENT || !pipeline_key->disable_sinking_load_input_fs) + sink_opts |= nir_move_load_input; + + nir_opt_sink(stages[i].nir, sink_opts); nir_opt_move(stages[i].nir, nir_move_load_input | nir_move_const_undef | nir_move_copies); /* Lower I/O intrinsics to memory instructions. */ @@ -4448,9 +4455,12 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout /* cleanup passes */ nir_lower_load_const_to_scalar(stages[i].nir); + + sink_opts |= nir_move_comparisons | nir_move_load_ubo | nir_move_load_ssbo; + nir_opt_sink(stages[i].nir, sink_opts); + nir_move_options move_opts = nir_move_const_undef | nir_move_load_ubo | nir_move_load_input | nir_move_comparisons | nir_move_copies; - nir_opt_sink(stages[i].nir, move_opts | nir_move_load_ssbo); nir_opt_move(stages[i].nir, move_opts); stages[i].feedback.duration += os_time_get_nano() - stage_start; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 4f2581c33d8..a5485b0a737 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -352,6 +352,7 @@ struct radv_instance { bool disable_htile_layers; bool disable_aniso_single_level; bool zero_vram; + bool disable_sinking_load_input_fs; }; VkResult radv_init_wsi(struct radv_physical_device *physical_device); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 862d9ba6482..3e74a56d0dc 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -63,6 +63,7 @@ struct radv_pipeline_key { uint32_t use_ngg : 1; uint32_t adjust_frag_coord_z : 1; uint32_t disable_aniso_single_level : 1; + uint32_t disable_sinking_load_input_fs : 1; struct { uint32_t instance_rate_inputs; diff --git a/src/util/driconf.h b/src/util/driconf.h index e580f6fe2d8..8bfabce676a 100644 --- a/src/util/driconf.h +++ b/src/util/driconf.h @@ -576,6 +576,10 @@ DRI_CONF_OPT_B(radv_disable_aniso_single_level, def, \ "Disable anisotropic filtering for single level images") +#define DRI_CONF_RADV_DISABLE_SINKING_LOAD_INPUT_FS(def) \ + DRI_CONF_OPT_B(radv_disable_sinking_load_input_fs, def, \ + "Disable sinking load inputs for fragment shaders") + /** * \brief ANV specific configuration options */
