Module: Mesa
Branch: main
Commit: 212f183c1f55c3e113cf8d5e6de38ace806c52f0
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=212f183c1f55c3e113cf8d5e6de38ace806c52f0

Author: Timur Kristóf <[email protected]>
Date:   Wed Mar 23 19:13:20 2022 +0100

ac/nir: Remove now-superfluous ac_nir_lower_tess_to_const.

Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13155>

---

 src/amd/common/ac_nir.h                      | 11 ------
 src/amd/common/ac_nir_lower_tess_io_to_mem.c | 56 ----------------------------
 src/amd/vulkan/radv_shader.c                 |  4 --
 3 files changed, 71 deletions(-)

diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h
index a68b8e7f24e..08f0cc0eed3 100644
--- a/src/amd/common/ac_nir.h
+++ b/src/amd/common/ac_nir.h
@@ -86,17 +86,6 @@ ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,
                                unsigned num_reserved_tcs_outputs,
                                unsigned num_reserved_tcs_patch_outputs);
 
-enum ac_nir_tess_to_const_options {
-    ac_nir_lower_patch_vtx_in = 1 << 0,
-    ac_nir_lower_num_patches = 1 << 1,
-};
-
-void
-ac_nir_lower_tess_to_const(nir_shader *shader,
-                           unsigned patch_vtx_in,
-                           unsigned tcs_num_patches,
-                           unsigned options);
-
 void
 ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
                                enum chip_class chip_class,
diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c 
b/src/amd/common/ac_nir_lower_tess_io_to_mem.c
index f55adec645f..e56e529bb10 100644
--- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c
+++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c
@@ -719,59 +719,3 @@ ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,
                                  lower_tes_input_load,
                                  &state);
 }
-
-typedef struct
-{
-   unsigned patch_vtx_in;
-   unsigned tcs_num_patches;
-   unsigned options;
-} lower_tess_to_const_state;
-
-static bool
-filter_const_lowerable_tess_intrinsics(const nir_instr *instr,
-                                       const void *state)
-{
-   if (instr->type != nir_instr_type_intrinsic)
-      return false;
-
-   lower_tess_to_const_state *st = (lower_tess_to_const_state *) state;
-   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-   return ((st->options & ac_nir_lower_patch_vtx_in) && intrin->intrinsic == 
nir_intrinsic_load_patch_vertices_in) ||
-          ((st->options & ac_nir_lower_num_patches) && intrin->intrinsic == 
nir_intrinsic_load_tcs_num_patches_amd);
-}
-
-static nir_ssa_def *
-lower_tess_intrinsics_to_const(nir_builder *b,
-                               nir_instr *instr,
-                               void *state)
-{
-   lower_tess_to_const_state *st = (lower_tess_to_const_state *) state;
-   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-
-   switch (intrin->intrinsic) {
-   case nir_intrinsic_load_patch_vertices_in:
-      return nir_imm_int(b, st->patch_vtx_in);
-   case nir_intrinsic_load_tcs_num_patches_amd:
-      return nir_imm_int(b, st->tcs_num_patches);
-   default:
-      unreachable("Unsupported tess intrinsic.");
-   }
-}
-
-void
-ac_nir_lower_tess_to_const(nir_shader *shader,
-                           unsigned patch_vtx_in,
-                           unsigned tcs_num_patches,
-                           unsigned options)
-{
-   lower_tess_to_const_state st = {
-      .patch_vtx_in = patch_vtx_in,
-      .tcs_num_patches = tcs_num_patches,
-      .options = options,
-   };
-
-   nir_shader_lower_instructions(shader,
-                                 filter_const_lowerable_tess_intrinsics,
-                                 lower_tess_intrinsics_to_const,
-                                 &st);
-}
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index ab97a48bfaf..b0b0b8b45f6 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1024,15 +1024,11 @@ radv_lower_io_to_mem(struct radv_device *device, struct 
radv_pipeline_stage *sta
          nir, device->physical_device->rad_info.chip_class, 
info->tcs.tes_reads_tess_factors,
          info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, 
info->tcs.num_linked_inputs,
          info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs, 
true);
-      ac_nir_lower_tess_to_const(nir, pl_key->tcs.tess_input_vertices, 
info->num_tess_patches,
-                                 ac_nir_lower_patch_vtx_in | 
ac_nir_lower_num_patches);
 
       return true;
    } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
       ac_nir_lower_tes_inputs_to_mem(nir, info->tes.num_linked_inputs,
                                      info->tes.num_linked_patch_inputs);
-      ac_nir_lower_tess_to_const(nir, nir->info.tess.tcs_vertices_out, 
info->num_tess_patches,
-                                 ac_nir_lower_patch_vtx_in | 
ac_nir_lower_num_patches);
 
       if (info->tes.as_es) {
          ac_nir_lower_es_outputs_to_mem(nir, 
device->physical_device->rad_info.chip_class,

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