Module: Mesa Branch: main Commit: 17fcbd874283442599f40f09107613aee1e754c1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=17fcbd874283442599f40f09107613aee1e754c1
Author: Dave Airlie <[email protected]> Date: Tue May 10 11:44:01 2022 +1000 ac: port radeonsi tess factor calculations to common code. This was updated in 4e49a05e37232 ("radeonsi: increase the tesselation factor ring size") and 9fecac091f315 ("radeonsi/gfx11: scattered register deltas") This will apply this to radv. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16415> --- src/amd/common/ac_gpu_info.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index e1f1022c52d..75a582514fe 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1763,7 +1763,7 @@ void ac_get_hs_info(struct radeon_info *info, bool double_offchip_buffers = info->chip_class >= GFX7 && info->family != CHIP_CARRIZO && info->family != CHIP_STONEY; - unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64; + unsigned max_offchip_buffers_per_se; unsigned max_offchip_buffers; unsigned offchip_granularity; unsigned hs_offchip_param; @@ -1783,12 +1783,16 @@ void ac_get_hs_info(struct radeon_info *info, * * Follow AMDVLK here. */ - if (info->chip_class >= GFX10) { + if (info->chip_class >= GFX11) { + max_offchip_buffers_per_se = 256; /* TODO: we could decrease this to reduce memory/cache usage */ + } else if (info->chip_class >= GFX10) { max_offchip_buffers_per_se = 128; - } else if (info->family == CHIP_VEGA10 || - info->chip_class == GFX7 || - info->chip_class == GFX6) - --max_offchip_buffers_per_se; + } else if (info->family == CHIP_VEGA12 || info->family == CHIP_VEGA20) { + /* Only certain chips can use the maximum value. */ + max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64; + } else { + max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63; + } max_offchip_buffers = max_offchip_buffers_per_se * info->max_se; @@ -1820,7 +1824,11 @@ void ac_get_hs_info(struct radeon_info *info, hs->max_offchip_buffers = max_offchip_buffers; - if (info->chip_class >= GFX10_3) { + if (info->chip_class >= GFX11) { + /* OFFCHIP_BUFFERING is per SE. */ + hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers_per_se - 1) | + S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity); + } else if (info->chip_class >= GFX10_3) { hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) | S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity); } else if (info->chip_class >= GFX7) { @@ -1834,7 +1842,7 @@ void ac_get_hs_info(struct radeon_info *info, hs->hs_offchip_param = hs_offchip_param; - hs->tess_factor_ring_size = 32768 * info->max_se; + hs->tess_factor_ring_size = 48 * 1024 * info->max_se; hs->tess_offchip_ring_offset = align(hs->tess_factor_ring_size, 64 * 1024); hs->tess_offchip_ring_size = hs->max_offchip_buffers * hs->tess_offchip_block_dw_size * 4; }
