Module: Mesa Branch: main Commit: d3a5f411a32864b69fbc764843679730d6de6273 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3a5f411a32864b69fbc764843679730d6de6273
Author: Pierre-Eric Pelloux-Prayer <[email protected]> Date: Thu Apr 14 13:32:03 2022 +0200 radeonsi: implement pipeline stats workaround DISABLE_INSTANCE_PACKING needs to be enabled when stats queries are active to fix incorrect results. We need to emit this for indexed and non-indexed draws. Based on PAL's waDisableInstancePacking. This fixes: KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861> --- .../drivers/radeonsi/ci/gfx10-navi10-fail.csv | 1 - .../radeonsi/ci/gfx10_3-sienna_cichlid-fail.csv | 1 - .../drivers/radeonsi/ci/gfx9-raven-fail.csv | 1 - src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.cpp | 30 ++++++++++++++++++++-- 5 files changed, 29 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv index 906784b16ca..8172d273f68 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv @@ -173,7 +173,6 @@ wgl@wgl-sanity,Fail # glcts failures KHR-GL46.gl_spirv.spirv_glsl_to_spirv_builtin_functions_test,Fail KHR-GL46.pipeline_statistics_query_tests_ARB.functional_geometry_shader_queries,Fail -KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives,Fail KHR-GL46.shader_ballot_tests.ShaderBallotFunctionRead,Fail KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks,Fail KHR-GL46.sparse_texture_tests.SparseTextureCommitment,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx10_3-sienna_cichlid-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx10_3-sienna_cichlid-fail.csv index 52693bfb52a..d57b7584574 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx10_3-sienna_cichlid-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx10_3-sienna_cichlid-fail.csv @@ -187,7 +187,6 @@ wgl@wgl-sanity,Fail # glcts failures KHR-GL46.pipeline_statistics_query_tests_ARB.functional_geometry_shader_queries,Fail -KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives,Fail KHR-GL46.shader_ballot_tests.ShaderBallotFunctionRead,Fail KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation,Fail KHR-GL46.sparse_texture2_tests.SparseTexture2Commitment,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx9-raven-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx9-raven-fail.csv index 173560ef9d7..b804aca1765 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx9-raven-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx9-raven-fail.csv @@ -263,7 +263,6 @@ wgl@wgl-sanity,Fail # glcts failures KHR-GL46.gl_spirv.spirv_glsl_to_spirv_builtin_functions_test,Fail KHR-GL46.pipeline_statistics_query_tests_ARB.functional_geometry_shader_queries,Fail -KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives,Fail KHR-GL46.packed_pixels.pbo_rectangle.r16_snorm,Fail KHR-GL46.packed_pixels.pbo_rectangle.r8_snorm,Fail KHR-GL46.packed_pixels.pbo_rectangle.rg16_snorm,Fail diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 8b5b82dd6cc..9cf0417721e 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1144,6 +1144,7 @@ struct si_context { /* Emitted draw state. */ bool ngg : 1; + bool disable_instance_packing : 1; uint16_t ngg_culling; unsigned last_index_size; int last_base_vertex; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index cf053b4d2e2..c87dbc74961 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -1460,13 +1460,30 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw uint32_t index_max_size = 0; uint64_t index_va = 0; + bool disable_instance_packing = false; radeon_begin(cs); + if (GFX_VERSION == GFX10_3) { + /* Workaround for incorrect stats with adjacent primitive types + * (see PAL's waDisableInstancePacking). + */ + if (sctx->num_pipeline_stat_queries && + sctx->shader.gs.cso == NULL && + (instance_count > 1 || indirect) && + (1 << info->mode) & (1 << PIPE_PRIM_LINES_ADJACENCY | + 1 << PIPE_PRIM_LINE_STRIP_ADJACENCY | + 1 << PIPE_PRIM_TRIANGLES_ADJACENCY | + 1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)) { + disable_instance_packing = true; + } + } + /* draw packet */ if (index_size) { /* Register shadowing doesn't shadow INDEX_TYPE. */ - if (index_size != sctx->last_index_size || sctx->shadowed_regs) { + if (index_size != sctx->last_index_size || sctx->shadowed_regs || + (GFX_VERSION == GFX10_3 && disable_instance_packing != sctx->disable_instance_packing)) { unsigned index_type; /* Index type computation. When we look at how we need to translate index_size, @@ -1476,7 +1493,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw * 2 = 010b --> 00b = 0 * 4 = 100b --> 01b = 1 */ - index_type = ((index_size >> 2) | (index_size << 1)) & 0x3; + index_type = (((index_size >> 2) | (index_size << 1)) & 0x3) | + S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing); if (GFX_VERSION <= GFX7 && SI_BIG_ENDIAN) { /* GFX7 doesn't support ubyte indices. */ @@ -1493,6 +1511,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw } sctx->last_index_size = index_size; + if (GFX_VERSION == GFX10_3) + sctx->disable_instance_packing = disable_instance_packing; } index_max_size = (indexbuf->width0 - index_offset) >> util_logbase2(index_size); @@ -1514,6 +1534,12 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw */ if (GFX_VERSION >= GFX7) sctx->last_index_size = -1; + if (GFX_VERSION == GFX10_3 && disable_instance_packing != sctx->disable_instance_packing) { + radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION, + R_03090C_VGT_INDEX_TYPE, 2, + S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing)); + sctx->disable_instance_packing = disable_instance_packing; + } } unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
