Module: Mesa Branch: main Commit: 69f5be8bad02d43c9501bced608c3b5af2d68952 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69f5be8bad02d43c9501bced608c3b5af2d68952
Author: Connor Abbott <[email protected]> Date: Wed Feb 16 17:56:15 2022 +0100 ir3: Add ir3_shader_variant::compiler And replace uses of ->shader->compiler. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16147> --- src/freedreno/ir3/ir3.c | 6 +++--- src/freedreno/ir3/ir3_assembler.c | 1 + src/freedreno/ir3/ir3_lower_parallelcopy.c | 8 ++++---- src/freedreno/ir3/ir3_nir.c | 14 +++++++------- src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c | 6 +++--- src/freedreno/ir3/ir3_nir_lower_tess.c | 2 +- src/freedreno/ir3/ir3_parser.y | 8 ++++---- src/freedreno/ir3/ir3_ra.c | 10 +++++----- src/freedreno/ir3/ir3_shader.c | 5 +++-- src/freedreno/ir3/ir3_shader.h | 9 +++++---- src/freedreno/ir3/ir3_spill.c | 2 +- src/gallium/drivers/freedreno/ir3/ir3_cmdline.c | 1 + src/gallium/drivers/freedreno/ir3/ir3_gallium.c | 2 +- 13 files changed, 39 insertions(+), 35 deletions(-) diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c index 8a2a7a004a1..facfdc89aa5 100644 --- a/src/freedreno/ir3/ir3.c +++ b/src/freedreno/ir3/ir3.c @@ -113,7 +113,7 @@ collect_reg_info(struct ir3_instruction *instr, struct ir3_register *reg, bool ir3_should_double_threadsize(struct ir3_shader_variant *v, unsigned regs_count) { - const struct ir3_compiler *compiler = v->shader->compiler; + const struct ir3_compiler *compiler = v->compiler; /* If the user forced a particular wavesize respect that. */ if (v->real_wavesize == IR3_SINGLE_ONLY) @@ -180,7 +180,7 @@ unsigned ir3_get_reg_independent_max_waves(struct ir3_shader_variant *v, bool double_threadsize) { - const struct ir3_compiler *compiler = v->shader->compiler; + const struct ir3_compiler *compiler = v->compiler; unsigned max_waves = compiler->max_waves; /* Compute the limit based on branchstack */ @@ -247,7 +247,7 @@ ir3_collect_info(struct ir3_shader_variant *v) { struct ir3_info *info = &v->info; struct ir3 *shader = v->ir; - const struct ir3_compiler *compiler = v->shader->compiler; + const struct ir3_compiler *compiler = v->compiler; memset(info, 0, sizeof(*info)); info->data = v; diff --git a/src/freedreno/ir3/ir3_assembler.c b/src/freedreno/ir3/ir3_assembler.c index f4777c32576..0b9c7efd99c 100644 --- a/src/freedreno/ir3/ir3_assembler.c +++ b/src/freedreno/ir3/ir3_assembler.c @@ -40,6 +40,7 @@ ir3_parse_asm(struct ir3_compiler *c, struct ir3_kernel_info *info, FILE *in) struct ir3_shader_variant *v = rzalloc_size(shader, sizeof(*v)); v->type = MESA_SHADER_COMPUTE; v->shader = shader; + v->compiler = c; v->const_state = rzalloc_size(v, sizeof(*v->const_state)); if (c->gen >= 6) diff --git a/src/freedreno/ir3/ir3_lower_parallelcopy.c b/src/freedreno/ir3/ir3_lower_parallelcopy.c index fbcd6ff62a6..433f6442832 100644 --- a/src/freedreno/ir3/ir3_lower_parallelcopy.c +++ b/src/freedreno/ir3/ir3_lower_parallelcopy.c @@ -482,7 +482,7 @@ handle_copies(struct ir3_shader_variant *v, struct ir3_instruction *instr, if (entries[i].flags & IR3_REG_SHARED) ctx.entries[ctx.entry_count++] = entries[i]; } - _handle_copies(v->shader->compiler, instr, &ctx); + _handle_copies(v->compiler, instr, &ctx); if (v->mergedregs) { /* Half regs and full regs are in the same file, so handle everything @@ -493,7 +493,7 @@ handle_copies(struct ir3_shader_variant *v, struct ir3_instruction *instr, if (!(entries[i].flags & IR3_REG_SHARED)) ctx.entries[ctx.entry_count++] = entries[i]; } - _handle_copies(v->shader->compiler, instr, &ctx); + _handle_copies(v->compiler, instr, &ctx); } else { /* There may be both half copies and full copies, so we have to split * them up since they don't interfere. @@ -503,14 +503,14 @@ handle_copies(struct ir3_shader_variant *v, struct ir3_instruction *instr, if (entries[i].flags & IR3_REG_HALF) ctx.entries[ctx.entry_count++] = entries[i]; } - _handle_copies(v->shader->compiler, instr, &ctx); + _handle_copies(v->compiler, instr, &ctx); ctx.entry_count = 0; for (unsigned i = 0; i < entry_count; i++) { if (!(entries[i].flags & (IR3_REG_HALF | IR3_REG_SHARED))) ctx.entries[ctx.entry_count++] = entries[i]; } - _handle_copies(v->shader->compiler, instr, &ctx); + _handle_copies(v->compiler, instr, &ctx); } } diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index 4ecc60e79bf..8ce844af77a 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -608,7 +608,7 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s) bool view_zero = so->key.view_zero && (s->info.inputs_read & VARYING_BIT_VIEWPORT); - if (so->key.ucp_enables && !so->shader->compiler->has_clip_cull) + if (so->key.ucp_enables && !so->compiler->has_clip_cull) progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, true); if (layer_zero || view_zero) progress |= OPT(s, ir3_nir_lower_view_layer_id, layer_zero, view_zero); @@ -632,7 +632,7 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s) * nir_opt_large_constants, because loading from a UBO is much, much less * expensive. */ - if (so->shader->compiler->has_pvtmem) { + if (so->compiler->has_pvtmem) { progress |= OPT(s, nir_lower_vars_to_scratch, nir_var_function_temp, 16 * 16 /* bytes */, glsl_get_natural_size_align_bytes); } @@ -657,7 +657,7 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s) * have to lower the preamble after UBO lowering so that UBO lowering can * insert instructions in the preamble to push UBOs. */ - if (so->shader->compiler->has_preamble && + if (so->compiler->has_preamble && !(ir3_shader_debug & IR3_DBG_NOPREAMBLE)) progress |= OPT(s, ir3_nir_opt_preamble, so); @@ -673,20 +673,20 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s) /* UBO offset lowering has to come after we've decided what will * be left as load_ubo */ - if (so->shader->compiler->gen >= 6) + if (so->compiler->gen >= 6) progress |= OPT(s, nir_lower_ubo_vec4); OPT_V(s, ir3_nir_lower_io_offsets); if (progress) - ir3_optimize_loop(so->shader->compiler, s); + ir3_optimize_loop(so->compiler, s); /* Fixup indirect load_uniform's which end up with a const base offset * which is too large to encode. Do this late(ish) so we actually * can differentiate indirect vs non-indirect. */ if (OPT(s, ir3_nir_fixup_load_uniform)) - ir3_optimize_loop(so->shader->compiler, s); + ir3_optimize_loop(so->compiler, s); /* Do late algebraic optimization to turn add(a, neg(b)) back into * subs, then the mandatory cleanup after algebraic. Note that it may @@ -834,7 +834,7 @@ void ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v, struct ir3_const_state *const_state) { - struct ir3_compiler *compiler = v->shader->compiler; + struct ir3_compiler *compiler = v->compiler; memset(&const_state->offsets, ~0, sizeof(const_state->offsets)); diff --git a/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c b/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c index e7a2bc1ba02..b4d2cd1ffa8 100644 --- a/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c +++ b/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c @@ -408,7 +408,7 @@ ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader_variant *v) { struct ir3_const_state *const_state = ir3_const_state(v); struct ir3_ubo_analysis_state *state = &const_state->ubo_state; - struct ir3_compiler *compiler = v->shader->compiler; + struct ir3_compiler *compiler = v->compiler; /* Limit our uploads to the amount of constant buffer space available in * the hardware, minus what the shader compiler may need for various @@ -464,7 +464,7 @@ ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader_variant *v) bool ir3_nir_lower_ubo_loads(nir_shader *nir, struct ir3_shader_variant *v) { - struct ir3_compiler *compiler = v->shader->compiler; + struct ir3_compiler *compiler = v->compiler; /* For the binning pass variant, we re-use the corresponding draw-pass * variants const_state and ubo state. To make these clear, in this * pass it is const (read-only) @@ -650,7 +650,7 @@ ir3_nir_lower_load_constant(nir_shader *nir, struct ir3_shader_variant *v) const_state); if (progress) { - struct ir3_compiler *compiler = v->shader->compiler; + struct ir3_compiler *compiler = v->compiler; /* Save a copy of the NIR constant data to the variant for * inclusion in the final assembly. diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c index 7ce254513a5..a038cd6c41e 100644 --- a/src/freedreno/ir3/ir3_nir_lower_tess.c +++ b/src/freedreno/ir3/ir3_nir_lower_tess.c @@ -357,7 +357,7 @@ ir3_nir_lower_to_explicit_input(nir_shader *shader, * HS uses a different primitive id, which starts at bit 16 in the header */ if (shader->info.stage == MESA_SHADER_TESS_CTRL && - v->shader->compiler->tess_use_shared) + v->compiler->tess_use_shared) state.local_primitive_id_start = 16; nir_function_impl *impl = nir_shader_get_entrypoint(shader); diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y index fd29c639da0..c306f9a7a6f 100644 --- a/src/freedreno/ir3/ir3_parser.y +++ b/src/freedreno/ir3/ir3_parser.y @@ -105,7 +105,7 @@ static struct ir3_instruction * new_instr(opc_t opc) static void new_shader(void) { - variant->ir = ir3_create(variant->shader->compiler, variant); + variant->ir = ir3_create(variant->compiler, variant); block = ir3_block_create(variant->ir); list_addtail(&block->node, &variant->ir->block_list); ip = 0; @@ -743,14 +743,14 @@ invocationid_header: T_A_INVOCATIONID '(' T_REGISTER ')' { wgid_header: T_A_WGID '(' T_REGISTER ')' { assert(($3 & 0x1) == 0); /* half-reg not allowed */ unsigned reg = $3 >> 1; - assert(variant->shader->compiler->gen >= 5); + assert(variant->compiler->gen >= 5); assert(reg >= regid(48, 0)); /* must be a high reg */ add_sysval(reg, 0x7, SYSTEM_VALUE_WORKGROUP_ID); } | T_A_WGID '(' T_CONSTANT ')' { assert(($3 & 0x1) == 0); /* half-reg not allowed */ unsigned reg = $3 >> 1; - assert(variant->shader->compiler->gen < 5); + assert(variant->compiler->gen < 5); info->wgid = reg; } @@ -759,7 +759,7 @@ numwg_header: T_A_NUMWG '(' T_CONSTANT ')' { unsigned reg = $3 >> 1; info->numwg = reg; /* reserve space in immediates for the actual value to be plugged in later: */ - if (variant->shader->compiler->gen >= 5) + if (variant->compiler->gen >= 5) add_const($3, 0, 0, 0, 0); } diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c index 96f944d0444..fccc3f384ba 100644 --- a/src/freedreno/ir3/ir3_ra.c +++ b/src/freedreno/ir3/ir3_ra.c @@ -2326,13 +2326,13 @@ calc_target_full_pressure(struct ir3_shader_variant *v, unsigned pressure) unsigned reg_independent_max_waves = ir3_get_reg_independent_max_waves(v, double_threadsize); unsigned reg_dependent_max_waves = ir3_get_reg_dependent_max_waves( - v->shader->compiler, reg_count, double_threadsize); + v->compiler, reg_count, double_threadsize); unsigned target_waves = MIN2(reg_independent_max_waves, reg_dependent_max_waves); while (target <= RA_FULL_SIZE / (2 * 4) && ir3_should_double_threadsize(v, target) == double_threadsize && - ir3_get_reg_dependent_max_waves(v->shader->compiler, target, + ir3_get_reg_dependent_max_waves(v->compiler, target, double_threadsize) >= target_waves) target++; @@ -2493,7 +2493,7 @@ static void calc_limit_pressure_for_cs_with_barrier(struct ir3_shader_variant *v, struct ir3_pressure *limit_pressure) { - const struct ir3_compiler *compiler = v->shader->compiler; + const struct ir3_compiler *compiler = v->compiler; unsigned threads_per_wg; if (v->local_size_variable) { @@ -2543,7 +2543,7 @@ ir3_ra(struct ir3_shader_variant *v) struct ra_ctx *ctx = rzalloc(NULL, struct ra_ctx); ctx->merged_regs = v->mergedregs; - ctx->compiler = v->shader->compiler; + ctx->compiler = v->compiler; ctx->stage = v->type; struct ir3_liveness *live = ir3_calc_liveness(ctx, v->ir); @@ -2590,7 +2590,7 @@ ir3_ra(struct ir3_shader_variant *v) bool spilled = false; if (max_pressure.full > limit_pressure.full || max_pressure.half > limit_pressure.half) { - if (!v->shader->compiler->has_pvtmem) { + if (!v->compiler->has_pvtmem) { d("max pressure exceeded!"); goto fail; } diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index 9fb6749a594..37eba7de827 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -129,7 +129,7 @@ fixup_regfootprint(struct ir3_shader_variant *v) void * ir3_shader_assemble(struct ir3_shader_variant *v) { - const struct ir3_compiler *compiler = v->shader->compiler; + const struct ir3_compiler *compiler = v->compiler; struct ir3_info *info = &v->info; uint32_t *bin; @@ -140,7 +140,7 @@ ir3_shader_assemble(struct ir3_shader_variant *v) * to indirectly upload from. */ info->constant_data_offset = - align(info->size, v->shader->compiler->const_upload_unit * 16); + align(info->size, v->compiler->const_upload_unit * 16); info->size = info->constant_data_offset + v->constant_data_size; } @@ -334,6 +334,7 @@ alloc_variant(struct ir3_shader *shader, const struct ir3_shader_key *key, v->nonbinning = nonbinning; v->key = *key; v->type = shader->type; + v->compiler = shader->compiler; v->mergedregs = shader->compiler->gen >= 6; v->stream_output = shader->stream_output; diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h index c6f912a822f..24c0203629f 100644 --- a/src/freedreno/ir3/ir3_shader.h +++ b/src/freedreno/ir3/ir3_shader.h @@ -530,6 +530,7 @@ struct ir3_shader_variant { /* replicated here to avoid passing extra ptrs everywhere: */ gl_shader_stage type; struct ir3_shader *shader; + struct ir3_compiler *compiler; char *name; @@ -896,7 +897,7 @@ ir3_const_state(const struct ir3_shader_variant *v) static inline unsigned ir3_max_const(const struct ir3_shader_variant *v) { - const struct ir3_compiler *compiler = v->shader->compiler; + const struct ir3_compiler *compiler = v->compiler; if ((v->type == MESA_SHADER_COMPUTE) || (v->type == MESA_SHADER_KERNEL)) { @@ -1151,15 +1152,15 @@ static inline uint32_t ir3_shader_branchstack_hw(const struct ir3_shader_variant *v) { /* Dummy shader */ - if (!v->shader) + if (!v->compiler) return 0; - if (v->shader->compiler->gen < 5) + if (v->compiler->gen < 5) return v->branchstack; if (v->branchstack > 0) { uint32_t branchstack = v->branchstack / 2 + 1; - return MIN2(branchstack, v->shader->compiler->branchstack_size / 2); + return MIN2(branchstack, v->compiler->branchstack_size / 2); } else { return 0; } diff --git a/src/freedreno/ir3/ir3_spill.c b/src/freedreno/ir3/ir3_spill.c index 90145c57202..84eef9446c9 100644 --- a/src/freedreno/ir3/ir3_spill.c +++ b/src/freedreno/ir3/ir3_spill.c @@ -514,7 +514,7 @@ spill_ctx_init(struct ra_spill_ctx *ctx, struct ir3_shader_variant *v, ctx->intervals[i] = &intervals[i]; ctx->intervals_count = ctx->live->definitions_count; - ctx->compiler = v->shader->compiler; + ctx->compiler = v->compiler; ctx->merged_regs = v->mergedregs; rb_tree_init(&ctx->reg_ctx.intervals); diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c index 6e8a01add9c..63cc1355100 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c @@ -426,6 +426,7 @@ main(int argc, char **argv) struct ir3_shader_variant *v = rzalloc_size(shader, sizeof(*v)); v->type = shader->type; v->shader = shader; + v->compiler = compiler; v->key = key; v->const_state = rzalloc_size(v, sizeof(*v->const_state)); diff --git a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c index c7c844274ee..2f40df26c81 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c @@ -102,7 +102,7 @@ dump_shader_info(struct ir3_shader_variant *v, static void upload_shader_variant(struct ir3_shader_variant *v) { - struct ir3_compiler *compiler = v->shader->compiler; + struct ir3_compiler *compiler = v->compiler; assert(!v->bo);
