Module: Mesa Branch: main Commit: 72625bea5fa25b4f82ba625599f1bf87c4f1ab2b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=72625bea5fa25b4f82ba625599f1bf87c4f1ab2b
Author: Benjamin Cheng <[email protected]> Date: Sun May 8 14:24:41 2022 -0400 radv: refactor image binding into struct Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16510> --- src/amd/vulkan/radv_cmd_buffer.c | 13 ++++++------ src/amd/vulkan/radv_descriptor_set.c | 4 ++-- src/amd/vulkan/radv_device.c | 31 ++++++++++++++++------------- src/amd/vulkan/radv_image.c | 32 ++++++++++++++++-------------- src/amd/vulkan/radv_meta_bufimage.c | 4 ++-- src/amd/vulkan/radv_meta_clear.c | 37 +++++++++++++++++++---------------- src/amd/vulkan/radv_meta_copy.c | 2 +- src/amd/vulkan/radv_meta_dcc_retile.c | 2 +- src/amd/vulkan/radv_meta_fast_clear.c | 2 +- src/amd/vulkan/radv_meta_fmask_copy.c | 7 ++++--- src/amd/vulkan/radv_private.h | 30 ++++++++++++++++------------ src/amd/vulkan/radv_sdma_copy_image.c | 2 +- 12 files changed, 90 insertions(+), 76 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 1b8f67cf366..a46c0b3b587 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2758,7 +2758,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) VkImageLayout layout = subpass->color_attachments[i].layout; bool in_render_loop = subpass->color_attachments[i].in_render_loop; - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->image->bo); + radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->image->bindings[0].bo); assert(iview->vk.aspects & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT)); @@ -2786,7 +2786,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop; struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview; radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, - cmd_buffer->state.attachments[idx].iview->image->bo); + cmd_buffer->state.attachments[idx].iview->image->bindings[0].bo); radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop); @@ -6403,12 +6403,12 @@ radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer, uint32_t subpa }; /* HTILE buffer */ - uint64_t htile_offset = ds_image->offset + ds_image->planes[0].surface.meta_offset + + uint64_t htile_offset = ds_image->bindings[0].offset + ds_image->planes[0].surface.meta_offset + ds_image->planes[0].surface.u.gfx9.meta_levels[level].offset; uint64_t htile_size = ds_image->planes[0].surface.u.gfx9.meta_levels[level].size; struct radv_buffer htile_buffer; - radv_buffer_init(&htile_buffer, cmd_buffer->device, ds_image->bo, htile_size, htile_offset); + radv_buffer_init(&htile_buffer, cmd_buffer->device, ds_image->bindings[0].bo, htile_size, htile_offset); /* Copy the VRS rates to the HTILE buffer. */ radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &extent, ds_image, &htile_buffer, true); @@ -9336,8 +9336,9 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, /* Initialize the mipmap levels without DCC. */ if (size != image->planes[0].surface.meta_size) { - flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, - radv_buffer_get_va(image->bo) + image->offset + + flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, + radv_buffer_get_va(image->bindings[0].bo) + + image->bindings[0].offset + image->planes[0].surface.meta_offset + size, image->planes[0].surface.meta_size - size, 0xffffffff); } diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 42729bdd588..1e56c72c366 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -1162,9 +1162,9 @@ write_image_descriptor(struct radv_device *device, struct radv_cmd_buffer *cmd_b memcpy(dst, descriptor, size); if (cmd_buffer) - radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->image->bo); + radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->image->bindings[0].bo); else - *buffer_list = iview->image->bo; + *buffer_list = iview->image->bindings[0].bo; } static ALWAYS_INLINE void diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 34719878170..54ee6dc775c 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -4778,7 +4778,7 @@ radv_sparse_image_opaque_bind_memory(struct radv_device *device, if (bind->pBinds[i].memory != VK_NULL_HANDLE) mem = radv_device_memory_from_handle(bind->pBinds[i].memory); - result = device->ws->buffer_virtual_bind(device->ws, image->bo, + result = device->ws->buffer_virtual_bind(device->ws, image->bindings[0].bo, bind->pBinds[i].resourceOffset, bind->pBinds[i].size, mem ? mem->bo : NULL, bind->pBinds[i].memoryOffset); if (result != VK_SUCCESS) @@ -4835,7 +4835,7 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem uint32_t aligned_extent_height = ALIGN(bind_extent.height, surface->prt_tile_height); uint32_t size = aligned_extent_width * aligned_extent_height * bs; - result = device->ws->buffer_virtual_bind(device->ws, image->bo, offset, size, + result = device->ws->buffer_virtual_bind(device->ws, image->bindings[0].bo, offset, size, mem ? mem->bo : NULL, mem_offset); if (result != VK_SUCCESS) return result; @@ -4844,8 +4844,8 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem uint32_t mem_increment = aligned_extent_width * bs; uint32_t size = mem_increment * surface->prt_tile_height; for (unsigned y = 0; y < bind_extent.height; y += surface->prt_tile_height) { - result = device->ws->buffer_virtual_bind( - device->ws, image->bo, offset + img_increment * y, size, mem ? mem->bo : NULL, + result = device->ws->buffer_virtual_bind(device->ws, + image->bindings[0].bo, offset + img_increment * y, size, mem ? mem->bo : NULL, mem_offset + mem_increment * y); if (result != VK_SUCCESS) return result; @@ -5348,7 +5348,7 @@ bool radv_get_memory_fd(struct radv_device *device, struct radv_device_memory *memory, int *pFD) { /* Only set BO metadata for the first plane */ - if (memory->image && memory->image->offset == 0) { + if (memory->image && memory->image->bindings[0].offset == 0) { struct radeon_bo_metadata metadata; radv_init_metadata(device, memory->image, &metadata); device->ws->buffer_set_metadata(device->ws, memory->bo, &metadata); @@ -5870,8 +5870,8 @@ radv_BindImageMemory2(VkDevice _device, uint32_t bindInfoCount, } } - image->bo = mem->bo; - image->offset = pBindInfos[i].memoryOffset; + image->bindings[0].bo = mem->bo; + image->bindings[0].offset = pBindInfos[i].memoryOffset; } return VK_SUCCESS; } @@ -6209,7 +6209,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff else cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1_GFX6(desc->swizzle[3] == PIPE_SWIZZLE_1); - va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; + va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset; cb->cb_color_base = va >> 8; @@ -6274,11 +6274,11 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff } /* CMASK variables */ - va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; + va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset; va += surf->cmask_offset; cb->cb_color_cmask = va >> 8; - va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; + va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset; va += surf->meta_offset; if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && @@ -6307,7 +6307,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff } if (radv_image_has_fmask(iview->image)) { - va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->fmask_offset; + va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset + + surf->fmask_offset; cb->cb_color_fmask = va >> 8; cb->cb_color_fmask |= surf->fmask_tile_swizzle; } else { @@ -6539,7 +6540,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf ds->db_htile_data_base = 0; ds->db_htile_surface = 0; - va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; + va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset; s_offs = z_offs = va; if (device->physical_device->rad_info.gfx_level >= GFX9) { @@ -6590,7 +6591,8 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1); } - va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->meta_offset; + va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset + + surf->meta_offset; ds->db_htile_data_base = va >> 8; ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1); @@ -6659,7 +6661,8 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1); } - va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->meta_offset; + va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset + + surf->meta_offset; ds->db_htile_data_base = va >> 8; ds->db_htile_surface = S_028ABC_FULL_CACHE(1); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index c837f267a27..51ce6c53571 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -766,7 +766,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im bool enable_write_compression, uint32_t *state) { struct radv_image_plane *plane = &image->planes[plane_id]; - uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; + struct radv_image_binding *binding = &image->bindings[0]; + uint64_t gpu_address = binding->bo ? radv_buffer_get_va(binding->bo) + binding->offset : 0; uint64_t va = gpu_address; enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; uint64_t meta_va = 0; @@ -1051,13 +1052,13 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima /* Initialize the sampler view for FMASK. */ if (fmask_state) { if (radv_image_has_fmask(image)) { - uint64_t gpu_address = radv_buffer_get_va(image->bo); + uint64_t gpu_address = radv_buffer_get_va(image->bindings[0].bo); uint32_t format; uint64_t va; assert(image->plane_count == 1); - va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; + va = gpu_address + image->bindings[0].offset + image->planes[0].surface.fmask_offset; switch (image->info.samples) { case 2: @@ -1090,7 +1091,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima fmask_state[7] = 0; if (radv_image_is_tc_compat_cmask(image)) { - va = gpu_address + image->offset + image->planes[0].surface.cmask_offset; + va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; fmask_state[6] |= S_00A018_COMPRESSION_EN(1); fmask_state[6] |= S_00A018_META_DATA_ADDRESS_LO(va >> 8); @@ -1230,12 +1231,12 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, if (fmask_state) { if (radv_image_has_fmask(image)) { uint32_t fmask_format; - uint64_t gpu_address = radv_buffer_get_va(image->bo); + uint64_t gpu_address = radv_buffer_get_va(image->bindings[0].bo); uint64_t va; assert(image->plane_count == 1); - va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; + va = gpu_address + image->bindings[0].offset + image->planes[0].surface.fmask_offset; if (device->physical_device->rad_info.gfx_level == GFX9) { fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK; @@ -1292,7 +1293,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) | S_008F24_META_RB_ALIGNED(1); if (radv_image_is_tc_compat_cmask(image)) { - va = gpu_address + image->offset + image->planes[0].surface.cmask_offset; + va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40); fmask_state[6] |= S_008F28_COMPRESSION_EN(1); @@ -1307,7 +1308,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer); if (radv_image_is_tc_compat_cmask(image)) { - va = gpu_address + image->offset + image->planes[0].surface.cmask_offset; + va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; fmask_state[6] |= S_008F28_COMPRESSION_EN(1); fmask_state[7] |= va >> 8; @@ -1369,7 +1370,7 @@ radv_init_metadata(struct radv_device *device, struct radv_image *image, if (device->physical_device->rad_info.gfx_level >= GFX9) { uint64_t dcc_offset = - image->offset + + image->bindings[0].offset + (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset); metadata->u.gfx9.swizzle_mode = surface->u.gfx9.swizzle_mode; metadata->u.gfx9.dcc_offset_256b = dcc_offset >> 8; @@ -1732,8 +1733,8 @@ static void radv_destroy_image(struct radv_device *device, const VkAllocationCallbacks *pAllocator, struct radv_image *image) { - if ((image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) && image->bo) - device->ws->buffer_destroy(device->ws, image->bo); + if ((image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) && image->bindings[0].bo) + device->ws->buffer_destroy(device->ws, image->bindings[0].bo); if (image->owned_memory != VK_NULL_HANDLE) { RADV_FROM_HANDLE(radv_device_memory, mem, image->owned_memory); @@ -1751,8 +1752,8 @@ radv_image_print_info(struct radv_device *device, struct radv_image *image) fprintf(stderr, " Info: size=%" PRIu64 ", alignment=%" PRIu32 ", " "width=%" PRIu32 ", height=%" PRIu32 ", " - "offset=%" PRIu64 ", array_size=%" PRIu32 ", levels=%" PRIu32 "\n", - image->size, image->alignment, image->info.width, image->info.height, image->offset, + "array_size=%" PRIu32 ", levels=%" PRIu32 "\n", + image->size, image->alignment, image->info.width, image->info.height, image->info.array_size, image->info.levels); for (unsigned i = 0; i < image->plane_count; ++i) { const struct radv_image_plane *plane = &image->planes[i]; @@ -1901,11 +1902,12 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_ if (image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) { image->alignment = MAX2(image->alignment, 4096); image->size = align64(image->size, image->alignment); - image->offset = 0; + image->bindings[0].offset = 0; result = device->ws->buffer_create(device->ws, image->size, image->alignment, 0, - RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL, 0, &image->bo); + RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL, 0, + &image->bindings[0].bo); if (result != VK_SUCCESS) { radv_destroy_image(device, alloc, image); return vk_error(device, result); diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 7ba611d5575..df14fe7cbf8 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -1249,7 +1249,7 @@ create_buffer_from_image(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl struct radv_device *device = cmd_buffer->device; struct radv_device_memory mem; - radv_device_memory_init(&mem, device, surf->image->bo); + radv_device_memory_init(&mem, device, surf->image->bindings[0].bo); radv_CreateBuffer(radv_device_to_handle(device), &(VkBufferCreateInfo){ @@ -1266,7 +1266,7 @@ create_buffer_from_image(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO, .buffer = *buffer, .memory = radv_device_memory_to_handle(&mem), - .memoryOffset = surf->image->offset, + .memoryOffset = surf->image->bindings[0].offset, }}); radv_device_memory_finish(&mem); diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index b79e46f5169..d909e28ace9 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1259,7 +1259,7 @@ uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value) { - uint64_t offset = image->offset + image->planes[0].surface.cmask_offset; + uint64_t offset = image->bindings[0].offset + image->planes[0].surface.cmask_offset; uint64_t size; if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { @@ -1272,15 +1272,15 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, size = slice_size * radv_get_layerCount(image, range); } - return radv_fill_buffer(cmd_buffer, image, image->bo, radv_buffer_get_va(image->bo) + offset, - size, value); + return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, + radv_buffer_get_va(image->bindings[0].bo) + offset, size, value); } uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value) { - uint64_t offset = image->offset + image->planes[0].surface.fmask_offset; + uint64_t offset = image->bindings[0].offset + image->planes[0].surface.fmask_offset; unsigned slice_size = image->planes[0].surface.fmask_slice_size; uint64_t size; @@ -1290,8 +1290,8 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, offset += slice_size * range->baseArrayLayer; size = slice_size * radv_get_layerCount(image, range); - return radv_fill_buffer(cmd_buffer, image, image->bo, radv_buffer_get_va(image->bo) + offset, - size, value); + return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, + radv_buffer_get_va(image->bindings[0].bo) + offset, size, value); } uint32_t @@ -1306,7 +1306,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, radv_update_dcc_metadata(cmd_buffer, image, range, true); for (uint32_t l = 0; l < level_count; l++) { - uint64_t offset = image->offset + image->planes[0].surface.meta_offset; + uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset; uint32_t level = range->baseMipLevel + l; uint64_t size; @@ -1338,8 +1338,9 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, if (!size) continue; - flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, - radv_buffer_get_va(image->bo) + offset, size, value); + flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, + radv_buffer_get_va(image->bindings[0].bo) + offset, + size, value); } return flush_bits; @@ -1474,7 +1475,7 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im /* Clear individuals levels separately. */ for (uint32_t l = 0; l < level_count; l++) { uint32_t level = range->baseMipLevel + l; - uint64_t offset = image->offset + image->planes[0].surface.meta_offset + + uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset + image->planes[0].surface.u.gfx9.meta_levels[level].offset; uint32_t size = image->planes[0].surface.u.gfx9.meta_levels[level].size; @@ -1484,28 +1485,30 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im if (htile_mask == UINT_MAX) { /* Clear the whole HTILE buffer. */ - flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, - radv_buffer_get_va(image->bo) + offset, size, value); + flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, + radv_buffer_get_va(image->bindings[0].bo) + offset, + size, value); } else { /* Only clear depth or stencil bytes in the HTILE buffer. */ flush_bits |= - clear_htile_mask(cmd_buffer, image, image->bo, offset, size, value, htile_mask); + clear_htile_mask(cmd_buffer, image, image->bindings[0].bo, offset, size, value, htile_mask); } } } else { unsigned layer_count = radv_get_layerCount(image, range); uint64_t size = image->planes[0].surface.meta_slice_size * layer_count; - uint64_t offset = image->offset + image->planes[0].surface.meta_offset + + uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset + image->planes[0].surface.meta_slice_size * range->baseArrayLayer; if (htile_mask == UINT_MAX) { /* Clear the whole HTILE buffer. */ - flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, - radv_buffer_get_va(image->bo) + offset, size, value); + flush_bits = radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, + radv_buffer_get_va(image->bindings[0].bo) + offset, + size, value); } else { /* Only clear depth or stencil bytes in the HTILE buffer. */ flush_bits = - clear_htile_mask(cmd_buffer, image, image->bo, offset, size, value, htile_mask); + clear_htile_mask(cmd_buffer, image, image->bindings[0].bo, offset, size, value, htile_mask); } } diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c index 501e6e70ff3..74404ce4a57 100644 --- a/src/amd/vulkan/radv_meta_copy.c +++ b/src/amd/vulkan/radv_meta_copy.c @@ -238,7 +238,7 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf assert(image->info.height == region->imageExtent.height); ASSERTED bool res = radv_sdma_copy_image(cmd_buffer, image, buffer, region); assert(res); - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo); + radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bindings[0].bo); radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, buffer->bo); return; } diff --git a/src/amd/vulkan/radv_meta_dcc_retile.c b/src/amd/vulkan/radv_meta_dcc_retile.c index 6067289ab32..8a79393c495 100644 --- a/src/amd/vulkan/radv_meta_dcc_retile.c +++ b/src/amd/vulkan/radv_meta_dcc_retile.c @@ -211,7 +211,7 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.dcc_retile.pipeline[swizzle_mode]); - radv_buffer_init(&buffer, device, image->bo, image->size, image->offset); + radv_buffer_init(&buffer, device, image->bindings[0].bo, image->size, image->bindings[0].offset); struct radv_buffer_view views[2]; VkBufferView view_handles[2]; diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index bfa23bfc8f7..4a62d0f7ed7 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -465,7 +465,7 @@ radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer, uint64_t va = 0; if (value) { - va = radv_buffer_get_va(image->bo) + image->offset; + va = radv_buffer_get_va(image->bindings[0].bo) + image->bindings[0].offset; va += pred_offset; } diff --git a/src/amd/vulkan/radv_meta_fmask_copy.c b/src/amd/vulkan/radv_meta_fmask_copy.c index 26b92504505..a2814453bb4 100644 --- a/src/amd/vulkan/radv_meta_fmask_copy.c +++ b/src/amd/vulkan/radv_meta_fmask_copy.c @@ -236,10 +236,11 @@ radv_fixup_copy_dst_metadata(struct radv_cmd_buffer *cmd_buffer, const struct ra /* Copy CMASK+FMASK. */ size = src_image->planes[0].surface.cmask_size + src_image->planes[0].surface.fmask_size; - src_offset = src_image->offset + src_image->planes[0].surface.fmask_offset; - dst_offset = dst_image->offset + dst_image->planes[0].surface.fmask_offset; + src_offset = src_image->bindings[0].offset + src_image->planes[0].surface.fmask_offset; + dst_offset = dst_image->bindings[0].offset + dst_image->planes[0].surface.fmask_offset; - radv_copy_buffer(cmd_buffer, src_image->bo, dst_image->bo, src_offset, dst_offset, size); + radv_copy_buffer(cmd_buffer, src_image->bindings[0].bo, dst_image->bindings[0].bo, + src_offset, dst_offset, size); } bool diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 9204ca670f0..77122242d44 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2372,6 +2372,12 @@ struct radv_image_plane { struct radeon_surf surface; }; +struct radv_image_binding { + /* Set when bound */ + struct radeon_winsys_bo *bo; + VkDeviceSize offset; +}; + struct radv_image { struct vk_image vk; @@ -2387,9 +2393,7 @@ struct radv_image { bool dcc_sign_reinterpret; bool support_comp_to_single; - /* Set when bound */ - struct radeon_winsys_bo *bo; - VkDeviceSize offset; + struct radv_image_binding bindings[3]; bool tc_compatible_cmask; uint64_t clear_value_offset; @@ -2555,8 +2559,8 @@ radv_image_get_fast_clear_va(const struct radv_image *image, uint32_t base_level { assert(radv_image_has_clear_value(image)); - uint64_t va = radv_buffer_get_va(image->bo); - va += image->offset + image->clear_value_offset + base_level * 8; + uint64_t va = radv_buffer_get_va(image->bindings[0].bo); + va += image->bindings[0].offset + image->clear_value_offset + base_level * 8; return va; } @@ -2565,8 +2569,8 @@ radv_image_get_fce_pred_va(const struct radv_image *image, uint32_t base_level) { assert(image->fce_pred_offset != 0); - uint64_t va = radv_buffer_get_va(image->bo); - va += image->offset + image->fce_pred_offset + base_level * 8; + uint64_t va = radv_buffer_get_va(image->bindings[0].bo); + va += image->bindings[0].offset + image->fce_pred_offset + base_level * 8; return va; } @@ -2575,8 +2579,8 @@ radv_image_get_dcc_pred_va(const struct radv_image *image, uint32_t base_level) { assert(image->dcc_pred_offset != 0); - uint64_t va = radv_buffer_get_va(image->bo); - va += image->offset + image->dcc_pred_offset + base_level * 8; + uint64_t va = radv_buffer_get_va(image->bindings[0].bo); + va += image->bindings[0].offset + image->dcc_pred_offset + base_level * 8; return va; } @@ -2585,8 +2589,8 @@ radv_get_tc_compat_zrange_va(const struct radv_image *image, uint32_t base_level { assert(image->tc_compat_zrange_offset != 0); - uint64_t va = radv_buffer_get_va(image->bo); - va += image->offset + image->tc_compat_zrange_offset + base_level * 4; + uint64_t va = radv_buffer_get_va(image->bindings[0].bo); + va += image->bindings[0].offset + image->tc_compat_zrange_offset + base_level * 4; return va; } @@ -2595,8 +2599,8 @@ radv_get_ds_clear_value_va(const struct radv_image *image, uint32_t base_level) { assert(radv_image_has_clear_value(image)); - uint64_t va = radv_buffer_get_va(image->bo); - va += image->offset + image->clear_value_offset + base_level * 8; + uint64_t va = radv_buffer_get_va(image->bindings[0].bo); + va += image->bindings[0].offset + image->clear_value_offset + base_level * 8; return va; } diff --git a/src/amd/vulkan/radv_sdma_copy_image.c b/src/amd/vulkan/radv_sdma_copy_image.c index 3bb2d077908..93044c6e675 100644 --- a/src/amd/vulkan/radv_sdma_copy_image.c +++ b/src/amd/vulkan/radv_sdma_copy_image.c @@ -76,7 +76,7 @@ radv_sdma_v4_v5_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct struct radv_device *device = cmd_buffer->device; unsigned bpp = image->planes[0].surface.bpe; uint64_t dst_address = buffer->bo->va; - uint64_t src_address = image->bo->va + image->planes[0].surface.u.gfx9.surf_offset; + uint64_t src_address = image->bindings[0].bo->va + image->planes[0].surface.u.gfx9.surf_offset; unsigned src_pitch = image->planes[0].surface.u.gfx9.surf_pitch; unsigned copy_width = DIV_ROUND_UP(image->info.width, image->planes[0].surface.blk_w); unsigned copy_height = DIV_ROUND_UP(image->info.height, image->planes[0].surface.blk_h);
