Module: Mesa Branch: main Commit: caed8df146288ead678a3388946437759ff69304 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=caed8df146288ead678a3388946437759ff69304
Author: Jason Ekstrand <[email protected]> Date: Mon Sep 7 01:21:23 2020 -0500 intel/fs_reg_allocate: Improve compressed instruction self-interference The old version worked fine for SIMD16 instructions but SIMD8 instructions where the destination spans two registers have the same problem. Reviewed-by: Caio Oliveira <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908> --- src/intel/compiler/brw_fs_reg_allocate.cpp | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp index cf37b5c4a9e..4f63f8ad50c 100644 --- a/src/intel/compiler/brw_fs_reg_allocate.cpp +++ b/src/intel/compiler/brw_fs_reg_allocate.cpp @@ -531,18 +531,18 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst) } } - /* In 16-wide instructions we have an issue where a compressed - * instruction is actually two instructions executed simultaneously. - * It's actually ok to have the source and destination registers be - * the same. In this case, each instruction over-writes its own - * source and there's no problem. The real problem here is if the - * source and destination registers are off by one. Then you can end - * up in a scenario where the first instruction over-writes the - * source of the second instruction. Since the compiler doesn't know - * about this level of granularity, we simply make the source and - * destination interfere. + /* A compressed instruction is actually two instructions executed + * simultaneously. On most platforms, it ok to have the source and + * destination registers be the same. In this case, each instruction + * over-writes its own source and there's no problem. The real problem + * here is if the source and destination registers are off by one. Then + * you can end up in a scenario where the first instruction over-writes the + * source of the second instruction. Since the compiler doesn't know about + * this level of granularity, we simply make the source and destination + * interfere. */ - if (inst->exec_size >= 16 && inst->dst.file == VGRF) { + if (inst->dst.component_size(inst->exec_size) > REG_SIZE && + inst->dst.file == VGRF) { for (int i = 0; i < inst->sources; ++i) { if (inst->src[i].file == VGRF) { ra_add_node_interference(g, first_vgrf_node + inst->dst.nr,
