Module: Mesa Branch: main Commit: 54bd5851ba8c0fd107b4498c7a6aa3220ca112fa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54bd5851ba8c0fd107b4498c7a6aa3220ca112fa
Author: Samuel Pitoiset <[email protected]> Date: Wed Aug 31 11:16:05 2022 +0200 radv: emit the LDS size for TCS directly from the pipeline on GFX9+ To be consistent with the LDS shader config for LS, and this will be emitted from the cmdbuf for dynamic patch control points. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timur Kristóf <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344> --- src/amd/vulkan/radv_pipeline.c | 8 +++++++- src/amd/vulkan/radv_shader.c | 6 ++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 46e445f601f..02ee4e279c8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -5022,15 +5022,21 @@ radv_pipeline_emit_hw_hs(struct radeon_cmdbuf *cs, const struct radv_graphics_pi uint64_t va = radv_shader_get_va(shader); if (pdevice->rad_info.gfx_level >= GFX9) { + uint32_t rsrc2 = shader->config.rsrc2; + if (pdevice->rad_info.gfx_level >= GFX10) { + rsrc2 |= S_00B42C_LDS_SIZE_GFX10(shader->info.tcs.num_lds_blocks); + radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); } else { + rsrc2 |= S_00B42C_LDS_SIZE_GFX9(shader->info.tcs.num_lds_blocks); + radeon_set_sh_reg(cs, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); } radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); radeon_emit(cs, shader->config.rsrc1); - radeon_emit(cs, shader->config.rsrc2); + radeon_emit(cs, rsrc2); } else { radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); radeon_emit(cs, va >> 8); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 34d7b6c2a5f..e1c9b7f8c46 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1726,12 +1726,10 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader } else if (pdevice->rad_info.gfx_level <= GFX10_3) { vgpr_comp_cnt = 1; } - config_out->rsrc2 |= - S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks) | S_00B42C_EXCP_EN_GFX6(excp_en); + config_out->rsrc2 |= S_00B42C_EXCP_EN_GFX6(excp_en); } else { vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; - config_out->rsrc2 |= - S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks) | S_00B42C_EXCP_EN_GFX9(excp_en); + config_out->rsrc2 |= S_00B42C_EXCP_EN_GFX9(excp_en); } } else { config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
