Module: Mesa Branch: staging/22.2 Commit: d424ca0ae948d5e90fcf6961f9d5bf7d6e243b48 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d424ca0ae948d5e90fcf6961f9d5bf7d6e243b48
Author: Lionel Landwerlin <[email protected]> Date: Wed Jun 8 11:04:31 2022 +0300 intel/fs: fixup scratch load/store handling on Gfx12.5+ We did not handle the operation with data size < 4. It works fine on all other messages (global/shared). The initial commit was just too restrictive. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 1e242785c315 ("intel/fs: Implement load/store_scratch on XeHP") Reviewed-by: Caio Oliveira <[email protected]> Reviewed-by: Ivan Briano <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964> (cherry picked from commit 3c78e94ff345fda6314e7644873d960c0ee97dc5) --- .pick_status.json | 2 +- src/intel/compiler/brw_fs_nir.cpp | 66 ++++++++++++++++++++------------------- 2 files changed, 35 insertions(+), 33 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index aaa391f3641..7798661be79 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -11452,7 +11452,7 @@ "description": "intel/fs: fixup scratch load/store handling on Gfx12.5+", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "1e242785c3155e71fec2ffcc7a814392ef9c90fe" }, diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5cafc75cd86..ea0677ac98a 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -5205,24 +5205,26 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr assert(nir_dest_num_components(instr->dest) == 1); assert(nir_dest_bit_size(instr->dest) <= 32); assert(nir_intrinsic_align(instr) > 0); - if (devinfo->verx10 >= 125) { - assert(nir_dest_bit_size(instr->dest) == 32 && - nir_intrinsic_align(instr) >= 4); + if (nir_dest_bit_size(instr->dest) == 32 && + nir_intrinsic_align(instr) >= 4) { + if (devinfo->verx10 >= 125) { + assert(nir_dest_bit_size(instr->dest) == 32 && + nir_intrinsic_align(instr) >= 4); - srcs[SURFACE_LOGICAL_SRC_ADDRESS] = - swizzle_nir_scratch_addr(bld, nir_addr, false); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_ADDRESS] = + swizzle_nir_scratch_addr(bld, nir_addr, false); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, - dest, srcs, SURFACE_LOGICAL_NUM_SRCS); - } else if (nir_dest_bit_size(instr->dest) == 32 && - nir_intrinsic_align(instr) >= 4) { - /* The offset for a DWORD scattered message is in dwords. */ - srcs[SURFACE_LOGICAL_SRC_ADDRESS] = - swizzle_nir_scratch_addr(bld, nir_addr, true); + bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, + dest, srcs, SURFACE_LOGICAL_NUM_SRCS); + } else { + /* The offset for a DWORD scattered message is in dwords. */ + srcs[SURFACE_LOGICAL_SRC_ADDRESS] = + swizzle_nir_scratch_addr(bld, nir_addr, true); - bld.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, - dest, srcs, SURFACE_LOGICAL_NUM_SRCS); + bld.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, + dest, srcs, SURFACE_LOGICAL_NUM_SRCS); + } } else { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = swizzle_nir_scratch_addr(bld, nir_addr, false); @@ -5276,27 +5278,27 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr assert(nir_src_bit_size(instr->src[0]) <= 32); assert(nir_intrinsic_write_mask(instr) == 1); assert(nir_intrinsic_align(instr) > 0); - if (devinfo->verx10 >= 125) { - assert(nir_src_bit_size(instr->src[0]) == 32 && - nir_intrinsic_align(instr) >= 4); - srcs[SURFACE_LOGICAL_SRC_DATA] = data; + if (nir_src_bit_size(instr->src[0]) == 32 && + nir_intrinsic_align(instr) >= 4) { + if (devinfo->verx10 >= 125) { + srcs[SURFACE_LOGICAL_SRC_DATA] = data; - srcs[SURFACE_LOGICAL_SRC_ADDRESS] = - swizzle_nir_scratch_addr(bld, nir_addr, false); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_ADDRESS] = + swizzle_nir_scratch_addr(bld, nir_addr, false); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, - dest, srcs, SURFACE_LOGICAL_NUM_SRCS); - } else if (nir_src_bit_size(instr->src[0]) == 32 && - nir_intrinsic_align(instr) >= 4) { - srcs[SURFACE_LOGICAL_SRC_DATA] = data; + bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, + dest, srcs, SURFACE_LOGICAL_NUM_SRCS); + } else { + srcs[SURFACE_LOGICAL_SRC_DATA] = data; - /* The offset for a DWORD scattered message is in dwords. */ - srcs[SURFACE_LOGICAL_SRC_ADDRESS] = - swizzle_nir_scratch_addr(bld, nir_addr, true); + /* The offset for a DWORD scattered message is in dwords. */ + srcs[SURFACE_LOGICAL_SRC_ADDRESS] = + swizzle_nir_scratch_addr(bld, nir_addr, true); - bld.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + bld.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, + fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + } } else { srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD); bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
