Module: Mesa Branch: staging/22.2 Commit: 3f3ecdccb1541cf209ce1a9c7e3fd0e06ced07d3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f3ecdccb1541cf209ce1a9c7e3fd0e06ced07d3
Author: Rhys Perry <[email protected]> Date: Thu Aug 4 17:54:56 2022 +0100 radv: fix 16-bit support in radv_lower_vs_input Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Fixes: b366fef091d ("radv: optimize the number of loaded components for VS inputs in NIR") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225> (cherry picked from commit 9ae13a9bd39e6b71ae0748d1cca598dce13f6306) --- .pick_status.json | 2 +- src/amd/vulkan/radv_pipeline.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 115accb6ebc..323bd822d83 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -9886,7 +9886,7 @@ "description": "radv: fix 16-bit support in radv_lower_vs_input", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "b366fef091d33e7d5307f292b2320267c841e350" }, diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 2407bd6e3d8..5490e159cea 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4241,9 +4241,10 @@ radv_lower_vs_input(nir_shader *nir, const struct radv_pipeline_key *pipeline_ke if (swizzle[i + component] < num_channels) { channels[i] = nir_channel(&b, &intrin->dest.ssa, swizzle[idx]); } else if (i + component == 3) { - channels[i] = is_float ? nir_imm_float(&b, 1.0f) : nir_imm_int(&b, 1u); + channels[i] = is_float ? nir_imm_floatN_t(&b, 1.0f, intrin->dest.ssa.bit_size) + : nir_imm_intN_t(&b, 1u, intrin->dest.ssa.bit_size); } else { - channels[i] = nir_imm_zero(&b, 1, 32); + channels[i] = nir_imm_zero(&b, 1, intrin->dest.ssa.bit_size); } }
