Module: Mesa
Branch: staging/22.2
Commit: 726e9bbf60e38734ac3c1191584a2c513f602481
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=726e9bbf60e38734ac3c1191584a2c513f602481

Author: Alyssa Rosenzweig <[email protected]>
Date:   Mon Aug 22 13:38:16 2022 -0400

pan/mdg: Print 3 sources for CSEL

The third source exists logically but not architecturally. We still need to
print it. Caught by the assertion.

Fixes: 0ee24c46e0a ("pan/mdg: Only print 2 sources for ALU")
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18338>
(cherry picked from commit 6fed6161876681920b0d2c59cb7413d7c43fda45)

---

 .pick_status.json                    |  2 +-
 src/panfrost/midgard/midgard_print.c | 18 ++++++++++++++++--
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 6cb06e3ad3c..07719bbff53 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -7465,7 +7465,7 @@
         "description": "pan/mdg: Print 3 sources for CSEL",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "0ee24c46e0aad500a4ef90cc03cfd319e11cb342"
     },
diff --git a/src/panfrost/midgard/midgard_print.c 
b/src/panfrost/midgard/midgard_print.c
index ed0d80b2c7e..06b92e032a5 100644
--- a/src/panfrost/midgard/midgard_print.c
+++ b/src/panfrost/midgard/midgard_print.c
@@ -293,8 +293,22 @@ mir_print_instruction(midgard_instruction *ins)
                 mir_print_src(ins, 1);
 
         if (is_alu) {
-                /* ALU ops are all 2-src */
-                assert(ins->src[2] == ~0);
+                /* ALU ops are all 2-src, though CSEL is treated like a 3-src
+                 * pseudo op with the third source scheduler lowered
+                 */
+                switch (ins->op) {
+                case midgard_alu_op_icsel:
+                case midgard_alu_op_fcsel:
+                case midgard_alu_op_icsel_v:
+                case midgard_alu_op_fcsel_v:
+                        printf(", ");
+                        mir_print_src(ins, 2);
+                        break;
+                default:
+                        assert(ins->src[2] == ~0);
+                        break;
+                }
+
                 assert(ins->src[3] == ~0);
         } else {
                 for (unsigned c = 2; c <= 3; ++c) {

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