Module: Mesa Branch: staging/22.2 Commit: 36ac6a48b99c9733153603e007c8f0b90853cbfb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36ac6a48b99c9733153603e007c8f0b90853cbfb
Author: Bas Nieuwenhuizen <[email protected]> Date: Fri Aug 19 14:55:54 2022 +0200 amd/common: Don't rely on DCN support checks with modifiers. Going to be a bad time if they disagree, which is bound to happen sometimes. Not asserting and stuff tends to be a better experience than crashing. Cc: mesa-stable Tested-by: Michel Dänzer <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18140> (cherry picked from commit af4b656817700ddcd4a26fdbf19a7b6dbbcd7738) --- .pick_status.json | 2 +- src/amd/common/ac_surface.c | 28 ++++++++++++++++++---------- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index fc8bdfe7f1c..2f03749511a 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -3379,7 +3379,7 @@ "description": "amd/common: Don't rely on DCN support checks with modifiers.", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 0f6d1b2d063..21e896334e6 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1873,14 +1873,19 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->tile_swizzle = xout.pipeBankXor; } + bool use_dcc = false; + if (surf->modifier != DRM_FORMAT_MOD_INVALID) { + use_dcc = ac_modifier_has_dcc(surf->modifier); + } else { + use_dcc = info->has_graphics && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && + is_dcc_supported_by_CB(info, in->swizzleMode) && + (!in->flags.display || + is_dcc_supported_by_DCN(info, config, surf, !in->flags.metaRbUnaligned, + !in->flags.metaPipeUnaligned)); + } + /* DCC */ - if (info->has_graphics && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && - is_dcc_supported_by_CB(info, in->swizzleMode) && - (!in->flags.display || - is_dcc_supported_by_DCN(info, config, surf, !in->flags.metaRbUnaligned, - !in->flags.metaPipeUnaligned)) && - (surf->modifier == DRM_FORMAT_MOD_INVALID || - ac_modifier_has_dcc(surf->modifier))) { + if (use_dcc) { ADDR2_COMPUTE_DCCINFO_INPUT din = {0}; ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0}; ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0}; @@ -2381,7 +2386,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ assert(is_dcc_supported_by_L2(info, surf)); if (AddrSurfInfoIn.flags.color) assert(is_dcc_supported_by_CB(info, surf->u.gfx9.swizzle_mode)); - if (AddrSurfInfoIn.flags.display) { + if (AddrSurfInfoIn.flags.display && surf->modifier == DRM_FORMAT_MOD_INVALID) { assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned, surf->u.gfx9.color.dcc.pipe_aligned)); } @@ -2392,8 +2397,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ (1 << surf->surf_alignment_log2) >= 64 * 1024 && /* 64KB tiling */ !(surf->flags & (RADEON_SURF_DISABLE_DCC | RADEON_SURF_FORCE_SWIZZLE_MODE | RADEON_SURF_FORCE_MICRO_TILE_MODE)) && - (surf->modifier == DRM_FORMAT_MOD_INVALID || - ac_modifier_has_dcc(surf->modifier)) && + surf->modifier == DRM_FORMAT_MOD_INVALID && is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned, surf->u.gfx9.color.dcc.pipe_aligned)) { /* Validate that DCC is enabled if DCN can do it. */ @@ -2412,6 +2416,10 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE; } + if (surf->modifier != DRM_FORMAT_MOD_INVALID) { + assert((surf->num_meta_levels != 0) == ac_modifier_has_dcc(surf->modifier)); + } + switch (surf->u.gfx9.swizzle_mode) { /* S = standard. */ case ADDR_SW_256B_S:
