Module: Mesa Branch: staging/22.2 Commit: 4698093affaecc67dd1be0dcc92d2172c73fc05e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4698093affaecc67dd1be0dcc92d2172c73fc05e
Author: Pierre-Eric Pelloux-Prayer <[email protected]> Date: Thu Sep 8 15:43:05 2022 +0200 radeonsi: invalidate L2 when using dcc stores This is only needed on chips with tcc_rb_non_coherent=1. Reviewed-by: Marek Olšák <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7084 Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18494> (cherry picked from commit 07a520f73168b1ee49e4baa68751b4e5a4c0d6ab) --- .pick_status.json | 2 +- src/gallium/drivers/radeonsi/si_compute_blit.c | 11 +++++++++++ src/gallium/drivers/radeonsi/si_state.c | 4 ++++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index 5038058cdac..0587b926a7c 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -499,7 +499,7 @@ "description": "radeonsi: invalidate L2 when using dcc stores", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index f31cf3a932f..1f290f70b0b 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -199,6 +199,17 @@ static void si_launch_grid_internal(struct si_context *sctx, const struct pipe_g sctx->flags |= sctx->gfx_level <= GFX8 ? SI_CONTEXT_WB_L2 : 0; /* Make sure image stores are visible to all CUs. */ sctx->flags |= SI_CONTEXT_INV_VCACHE; + /* Make sure RBs see our DCC changes. */ + if (sctx->gfx_level >= GFX10 && sctx->screen->info.tcc_rb_non_coherent) { + unsigned enabled_mask = sctx->images[PIPE_SHADER_COMPUTE].enabled_mask; + while (enabled_mask) { + int i = u_bit_scan(&enabled_mask); + if (sctx->images[PIPE_SHADER_COMPUTE].views[i].access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE) { + sctx->flags |= SI_CONTEXT_INV_L2; + break; + } + } + } } else { /* Make sure buffer stores are visible to all CUs. */ sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE | SI_CONTEXT_PFP_SYNC_ME; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 99f220b33a7..b0ab295c070 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5359,6 +5359,10 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) * automatically at end of shader, but the contents of other * L1 caches might still be stale. */ sctx->flags |= SI_CONTEXT_INV_VCACHE; + + if (flags & (PIPE_BARRIER_IMAGE | PIPE_BARRIER_TEXTURE) && + sctx->screen->info.tcc_rb_non_coherent) + sctx->flags |= SI_CONTEXT_INV_L2; } if (flags & PIPE_BARRIER_INDEX_BUFFER) {
