Module: Mesa Branch: main Commit: 1119e06a45a2bbd043087a52bf1a95a2b1aac01c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1119e06a45a2bbd043087a52bf1a95a2b1aac01c
Author: Qiang Yu <[email protected]> Date: Thu Jun 30 17:56:50 2022 +0800 nir,ac/llvm: add nir_intrinsic_load_ordered_id_amd Reviewed-by: Timur Kristóf <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654> --- src/amd/llvm/ac_nir_to_llvm.c | 3 +++ src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 3 +++ 3 files changed, 7 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 83e89ae54ae..2577c2719ad 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3616,6 +3616,9 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_user_clip_plane: result = ctx->abi->load_user_clip_plane(ctx->abi, nir_intrinsic_ucp_id(instr)); break; + case nir_intrinsic_load_ordered_id_amd: + result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info), 0, 12); + break; case nir_intrinsic_load_vertex_id_zero_base: result = ctx->abi->vertex_id_replaced ? ctx->abi->vertex_id_replaced : ctx->abi->vertex_id; break; diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 55f5df81e66..1fe64c930ca 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -185,6 +185,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_clip_half_line_width_amd: case nir_intrinsic_load_num_vertices_per_primitive_amd: case nir_intrinsic_load_streamout_buffer_amd: + case nir_intrinsic_load_ordered_id_amd: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 39ae64fd1a9..92c6adbbed9 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1431,6 +1431,9 @@ system_value("num_vertices_per_primitive_amd", 1) # BASE = buffer index intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) +# An ID for each workgroup ordered by primitve sequence +system_value("ordered_id_amd", 1) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel
