Module: Mesa Branch: main Commit: 058174c4ded714a047ce58dbbdc0eedc54a83d64 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=058174c4ded714a047ce58dbbdc0eedc54a83d64
Author: Georg Lehmann <[email protected]> Date: Tue Oct 4 15:08:06 2022 +0200 aco: Implement [ui]find_msb_rev. Signed-off-by: Georg Lehmann <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951> --- src/amd/compiler/aco_instruction_selection.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index aa4ab7b3f04..74287e1609f 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -1822,6 +1822,22 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } break; } + case nir_op_ufind_msb_rev: + case nir_op_ifind_msb_rev: { + Temp src = get_alu_src(ctx, instr->src[0]); + if (src.regClass() == s1) { + aco_opcode op = instr->op == nir_op_ufind_msb_rev ? aco_opcode::s_flbit_i32_b32 + : aco_opcode::s_flbit_i32; + bld.sop1(op, Definition(dst), src); + } else if (src.regClass() == v1) { + aco_opcode op = + instr->op == nir_op_ufind_msb_rev ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32; + emit_vop1_instruction(ctx, instr, op, dst); + } else { + isel_err(&instr->instr, "Unimplemented NIR instr bit size"); + } + break; + } case nir_op_uclz: { Temp src = get_alu_src(ctx, instr->src[0]); if (src.regClass() == s1) {
