Module: Mesa Branch: main Commit: c5bf63753d7b1e61d4529fe2dc5a81c49c8bbd45 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5bf63753d7b1e61d4529fe2dc5a81c49c8bbd45
Author: Samuel Pitoiset <[email protected]> Date: Thu Oct 20 04:40:50 2022 +0000 ac/nir,radv/llvm: add support for the attribute ring Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19216> --- src/amd/llvm/ac_nir_to_llvm.c | 1 + src/amd/vulkan/radv_nir_to_llvm.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 9ab8d0d58a4..0bbdc617cfc 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3605,6 +3605,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_ring_tess_offchip_offset_amd: case nir_intrinsic_load_ring_esgs_amd: case nir_intrinsic_load_ring_es2gs_offset_amd: + case nir_intrinsic_load_ring_attr_amd: case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_tcs_num_patches_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd: diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 1cd57a1999c..f8e7c244e82 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -66,6 +66,7 @@ struct radv_shader_context { LLVMValueRef gsvs_ring[4]; LLVMValueRef hs_ring_tess_offchip; LLVMValueRef hs_ring_tess_factor; + LLVMValueRef attr_ring; uint64_t output_mask; }; @@ -1257,6 +1258,14 @@ ac_setup_rings(struct radv_shader_context *ctx) ctx->hs_ring_tess_factor = ac_build_load_to_sgpr( &ctx->ac, ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false)); } + + if (ctx->options->gfx_level >= GFX11 && + ((ctx->stage == MESA_SHADER_VERTEX && !ctx->shader_info->vs.as_es && !ctx->shader_info->vs.as_ls) || + (ctx->stage == MESA_SHADER_TESS_EVAL && !ctx->shader_info->tes.as_es) || + (ctx->stage == MESA_SHADER_GEOMETRY))) { + ctx->attr_ring = ac_build_load_to_sgpr(&ctx->ac, ring_offsets, + LLVMConstInt(ctx->ac.i32, RING_PS_ATTR, false)); + } } /* Fixup the HW not emitting the TCS regs if there are no HS threads. */ @@ -1321,6 +1330,8 @@ static LLVMValueRef radv_intrinsic_load(struct ac_shader_abi *abi, nir_intrinsic return ctx->hs_ring_tess_offchip; case nir_intrinsic_load_ring_esgs_amd: return ctx->esgs_ring; + case nir_intrinsic_load_ring_attr_amd: + return ctx->attr_ring; default: return NULL; }
