Module: Mesa Branch: main Commit: c445c29263471af975f182ada36ca6311e8763c3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c445c29263471af975f182ada36ca6311e8763c3
Author: Alyssa Rosenzweig <[email protected]> Date: Wed Nov 30 12:51:41 2022 -0500 asahi: Use PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY The hardware only supports aligned loads and stores. That applies to vertex buffer loads as well. As such, we need to ensure that the base address of vertex buffers, the stride, and the offset are all aligned to the vertex buffer format, ensuring that the load itself is aligned. Mesa has a CAP for that, PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY, which ensures that these conditions are met and will rewrite a vertex buffer on the CPU in the off chance that they're not. This is a bug fix compared to the old code, because it requires that offsets and base addresses are aligned (not just the strides like before). It's also an optimization compared to the old code, because it does not require 4 byte alignment for 8-bit and 16-bit formats. In fact, it doesn't require any alignment for 8-bit formats. This will avoid needless CPU work for smaller formats. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996> --- src/gallium/drivers/asahi/agx_pipe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c index fccf7b1c8cd..1334e501ba0 100644 --- a/src/gallium/drivers/asahi/agx_pipe.c +++ b/src/gallium/drivers/asahi/agx_pipe.c @@ -1318,7 +1318,7 @@ agx_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: return 64; - case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: + case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY: return 1; case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
