Module: Mesa Branch: main Commit: 73ea7d651a5098248ae7040c9ac136379b15fcb8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=73ea7d651a5098248ae7040c9ac136379b15fcb8
Author: Qiang Yu <[email protected]> Date: Wed Aug 10 14:48:18 2022 +0800 ac/llvm: nir_load_smem_amd support 32bit base address For radeonsi which use 32bit address in ac_build_load_to_sgpr(). Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010> --- src/amd/llvm/ac_nir_to_llvm.c | 10 ++++++++-- src/compiler/nir/nir_intrinsics.py | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 310aa29a378..23140cb5d93 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -4386,11 +4386,17 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins LLVMValueRef base = get_src(ctx, instr->src[0]); LLVMValueRef offset = get_src(ctx, instr->src[1]); + bool is_addr_32bit = nir_src_bit_size(instr->src[0]) == 32; + int addr_space = is_addr_32bit ? AC_ADDR_SPACE_CONST_32BIT : AC_ADDR_SPACE_CONST; + LLVMTypeRef result_type = get_def_type(ctx, &instr->dest.ssa); - LLVMTypeRef byte_ptr_type = LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST); + LLVMTypeRef byte_ptr_type = LLVMPointerType(ctx->ac.i8, addr_space); LLVMValueRef addr = LLVMBuildIntToPtr(ctx->ac.builder, base, byte_ptr_type, ""); - addr = LLVMBuildGEP2(ctx->ac.builder, ctx->ac.i8, addr, &offset, 1, ""); + /* see ac_build_load_custom() for 32bit/64bit addr GEP difference */ + addr = is_addr_32bit ? + LLVMBuildInBoundsGEP2(ctx->ac.builder, ctx->ac.i8, addr, &offset, 1, "") : + LLVMBuildGEP2(ctx->ac.builder, ctx->ac.i8, addr, &offset, 1, ""); LLVMSetMetadata(addr, ctx->ac.uniform_md_kind, ctx->ac.empty_md); result = LLVMBuildLoad2(ctx->ac.builder, result_type, addr, ""); diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index dad90ab4e78..64e8ae0dfa3 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1477,7 +1477,7 @@ intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_EL intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER]) intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER]) -# src[] = { 64-bit base address, 32-bit offset }. +# src[] = { 32/64-bit base address, 32-bit offset }. intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32], indices=[ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE, CAN_REORDER])
