Module: Mesa Branch: main Commit: bb837bf6ef66c63474182ea7287939e995ed9901 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb837bf6ef66c63474182ea7287939e995ed9901
Author: Qiang Yu <[email protected]> Date: Thu Aug 11 10:17:16 2022 +0800 nir,ac/llvm: add nir_buffer_atomic_add_amd Used by radeonsi for lower nir_atomic_add_gen/xfb_prim_count_amd. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010> --- src/amd/llvm/ac_nir_to_llvm.c | 20 ++++++++++++++++++++ src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 3 +++ 3 files changed, 24 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 1b2a42783e3..c092aa1f523 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -4315,6 +4315,26 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gds_base, store_val, "workgroup-one-as"); break; } + case nir_intrinsic_buffer_atomic_add_amd: { + LLVMValueRef desc = get_src(ctx, instr->src[0]); + LLVMValueRef data = get_src(ctx, instr->src[1]); + unsigned base = nir_intrinsic_base(instr); + LLVMTypeRef return_type = LLVMTypeOf(data); + + LLVMValueRef args[] = { + data, desc, + LLVMConstInt(ctx->ac.i32, base, false), + ctx->ac.i32_0, /* soffset */ + ctx->ac.i32_0, /* cachepolicy */ + }; + + char name[64], type[8]; + ac_build_type_name_for_intr(return_type, type, sizeof(type)); + snprintf(name, sizeof(name), "llvm.amdgcn.raw.buffer.atomic.add.%s", type); + + result = ac_build_intrinsic(&ctx->ac, name, return_type, args, 5, 0); + break; + } case nir_intrinsic_export_vertex_amd: ctx->abi->export_vertex(ctx->abi); break; diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 40d6f1666ad..03712915a6e 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -652,6 +652,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_packed_passthrough_primitive_amd: case nir_intrinsic_load_initial_edgeflags_amd: case nir_intrinsic_gds_atomic_add_amd: + case nir_intrinsic_buffer_atomic_add_amd: case nir_intrinsic_load_rt_arg_scratch_offset_amd: case nir_intrinsic_load_intersection_opaque_amd: case nir_intrinsic_load_vector_arg_amd: diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 937185ce306..dbb0ef4b449 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1332,6 +1332,9 @@ store("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET, WRIT # Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0} intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) +# src[] = { descriptor, add_value } +intrinsic("buffer_atomic_add_amd", src_comp=[4, 1], dest_comp=1, indices=[BASE]) + # src[] = { sample_id, num_samples } intrinsic("load_sample_positions_amd", src_comp=[1, 1], dest_comp=2, flags=[CAN_ELIMINATE, CAN_REORDER])
